Abstract: An antenna assembly is provided having passive cooling elements that enable compact design. In one example, an antenna assembly is provided that includes a heat sink assembly having an interior side and an exterior side, an antenna array, an antenna circuit board, and a radome. The antenna circuit board includes at least one integrated circuit (IC) die. The IC die has a conductive primary heat dissipation path to the interior side of the heat sink assembly. The radome is coupled to the heat sink assembly and encloses the antenna circuit board and the antenna array between the radome and the heat sink assembly. The heat sink assembly includes a metal base plate and at least a first heat pipe embedded with the metal base plate. The first heat pipe is disposed between the metal base plate and the IC die.

Abstract: A cooling plate assembly and electronic device having the same are provided which utilize active and passive cooling devices for improved thermal management of one or more chip package assemblies included in the electronic device. In one example, a cooling plate assembly is provided that includes a cooling plate having a first surface and an opposing second surface, a first active cooling device coupled to the first surface of the cooling plate, and a first passive cooling device coupled to the second surface of the cooling plate.

Abstract: Some examples described herein provide for three-dimensional (3D) thermal management apparatuses for thermal energy dissipation of thermal energy generated by an electronic device. In an example, an apparatus includes a thermal management apparatus that includes a primary base, a passive two-phase flow thermal carrier, and fins. The thermal carrier has a carrier base and one or more sidewalls extending from the carrier base. The carrier base and the one or more sidewalls are a single integral piece. The primary base is attached to the thermal carrier. The carrier base has an exterior surface that at least a portion of which defines a die contact region. The thermal carrier has an internal volume aligned with the die contact region. A fluid is disposed in the internal volume. The fins are attached to and extend from the one or more sidewalls of the thermal carrier.

Abstract: Chip packages and electronic devices are provided that include a thermal capacitance element that improves the operation of IC dies at elevated temperatures. In one example, a chip package is provided that includes an integrated circuit (IC) die, a lid thermally connected to the IC die, and a thermal capacitance element thermally connected to the lid. The thermal capacitance element includes a container and a capacitance material sealingly disposed in the container. The capacitance material has a phase transition temperature that is between 80 and 100 percent of a maximum designed operating temperature in degrees Celsius of the IC die.

Abstract: Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a solid state electronic assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate and a heat sink mounted over the first IC die. The heat sink includes a thermally conductive plate and a first thermal carrier. The first thermal carrier has a first end mechanically fixed to the conductive plate. The first thermal carrier has a second end cantilevered from the conductive plate. The second end is in conductive contact with a top surface of the first IC die.

Abstract: Chip packages and electronic devices are provided that include a heat sink flexibly interfaced with a die for enhanced temperature control. In one example, a solid state electronic assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate and a heat sink mounted over the first IC die. The heat sink includes a thermally conductive plate and a first thermal carrier. The first thermal carrier has a first end mechanically fixed to the conductive plate. The first thermal carrier has a second end cantilevered from the conductive plate. The second end is in conductive contact with a top surface of the first IC die.

Abstract: An apparatus relates generally to serializer-deserializers. In such an apparatus, a first serializer-deserializer has a first data path and a data eye path. The first data path is coupled to a first data out interface of the first serializer-deserializer. A second serializer-deserializer has a second data path. The second data path is coupled to a second data out interface of the second serializer-deserializer. The data eye path of the first serializer-deserializer is coupled to the second data path of the second serializer-deserializer.

Abstract: An apparatus relates generally to serializer-deserializers. In such an apparatus, a first serializer-deserializer has a first data path and a data eye path. The first data path is coupled to a first data out interface of the first serializer-deserializer. A second serializer-deserializer has a second data path. The second data path is coupled to a second data out interface of the second serializer-deserializer. The data eye path of the first serializer-deserializer is coupled to the second data path of the second serializer-deserializer.

Abstract: A method for plesiochronous clock generation for parallel wireline transceivers, includes: inputting, into at least one decoder, at least one digital frequency mismatch number; decoding, with the at least one decoder, the at least one digital frequency mismatch number to obtain at least one digital frequency divider number that represents a transmit frequency associated with at least one signal; inputting the at least one digital frequency divider number into at least one fractional-N phase lock loop; and utilizing, by the at least one fractional-N phase lock loop, the at least one digital frequency divider number and an analog reference signal produced by a reference oscillator to produce a resultant signal at the transmit frequency; wherein the at least one decoder and the at least one fractional-N phase lock loop are contained on a single integrated circuit.

Abstract: A data-communications switch having at least two modes of operation is provided. The data communications switch includes a first Clos switch having a first mode of operation and a second Clos switch, which is combined with the first Clos switch, for providing a second mode of operation. The first Clos switch and second Clos switch are interconnected in an overlapping manner to form a switch fabric, which is essentially a superset of both the first Clos switch and the second Clos switch and can be configured to operate in either mode depending on system requirements.

Abstract: A data-communications switch having at least two modes of operation is provided. The data communications switch includes a first Clos switch having a first mode of operation and a second Clos switch, which is combined with the first Clos switch, for providing a second mode of operation. The first Clos switch and second Clos switch are interconnected in an overlapping manner to form a switch fabric, which is essentially a superset of both the first Clos switch and the second Clos switch and can be configured to operate in either mode depending on system requirements.