Patents by Inventor Anthony Willis Rich
Anthony Willis Rich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7793261Abstract: An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.Type: GrantFiled: October 1, 1999Date of Patent: September 7, 2010Assignee: STMicroelectronics LimitedInventors: David Alan Edwards, Margaret Rose Gearty, Glenn A. Farrall, Atsushi Hasegawa, Anthony Willis Rich
-
Patent number: 6918065Abstract: A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.Type: GrantFiled: October 1, 1999Date of Patent: July 12, 2005Assignee: Hitachi, Ltd.Inventors: David Alan Edwards, Anthony Willis Rich
-
Patent number: 6859891Abstract: An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.Type: GrantFiled: October 1, 1999Date of Patent: February 22, 2005Assignee: STMicroelectronics LimitedInventors: David Alan Edwards, Margaret Rose Gearty, Bernard Ramanadin, Anthony Willis Rich
-
Patent number: 6684348Abstract: A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.Type: GrantFiled: October 1, 1999Date of Patent: January 27, 2004Assignee: Hitachi, Ltd.Inventors: David Alan Edwards, Anthony Willis Rich
-
Patent number: 6615370Abstract: A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.Type: GrantFiled: October 1, 1999Date of Patent: September 2, 2003Assignee: Hitachi, Ltd.Inventors: David Alan Edwards, Anthony Willis Rich
-
Patent number: 6601189Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.Type: GrantFiled: October 1, 1999Date of Patent: July 29, 2003Assignee: STMicroelectronics LimitedInventors: David Alan Edwards, Anthony Willis Rich, Bernard Ramanadin
-
Patent number: 6591369Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.Type: GrantFiled: October 1, 1999Date of Patent: July 8, 2003Assignee: STMicroelectronics, Ltd.Inventors: David Alan Edwards, Anthony Willis Rich
-
Publication number: 20030115506Abstract: An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.Type: ApplicationFiled: October 1, 1999Publication date: June 19, 2003Inventors: DAVID ALAN EDWARDS, MARGARET ROSE GEARTY, BERNARD RAMANADIN, ANTHONY WILLIS RICH
-
Patent number: 6567932Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.Type: GrantFiled: October 1, 1999Date of Patent: May 20, 2003Assignee: STMicroelectronics LimitedInventors: David Alan Edwards, Anthony Willis Rich
-
Patent number: 6557119Abstract: A computer system, comprising at least one central processing unit and a memory unit coupled to the at least one central processing unit, a set of watchpoints defined in the computer system; each watchpoint in the set of watchpoints comprising a programmable precondition register and a programmable action register, a set of latches, and selection circuitry that selects one latch in the set of latches to couple an output of an action register to an input of the selected latch.Type: GrantFiled: October 1, 1999Date of Patent: April 29, 2003Assignee: STMicroelectronics LimitedInventors: David Alan Edwards, Anthony Willis Rich
-
Publication number: 20030056154Abstract: A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices io attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor.Type: ApplicationFiled: October 1, 1999Publication date: March 20, 2003Inventors: David Alan Edwards, Anthony Willis Rich