Abstract: A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.

Abstract: A driver circuit formed from CMOS material is provided for receiving an input logic signal from an internal CMOS circuit and inducing a corresponding output signal onto a terminated transmission line. The driver circuit comprises a pre-driver inverter having an input and an output. The inverter inverts a logic state of the input logic signal. The driver circuit also includes an output transistor that provides the output signal and has a drain electrically connected to the transmission line. The driver circuit also includes a control circuit for controlling the output signal during a transition of the input logic signal from a first logic state to a second logic state. The driver circuit is physically isolated from the internal CMOS circuit.

Abstract: An electronic system such as a Single-Chip-Module (SCM), a Multi-Chip-Module (MCM), or a Board-Level-Product (BLP) includes a plurality of units which are interconnected by a terminated transmission bus line. Each unit includes a CMOS circuit, a terminated bus line for signal transmission, and a driver/receiver circuit which is spaced from the CMOS circuit on a substrate. A guard ring is formed around at least a part of the CMOS circuit which faces the driver/receiver circuit. The driver/receiver circuit includes a driver for receiving an input logic signal from the CMOS circuit and inducing a corresponding signal onto the bus line, and a receiver for receiving an output signal from the bus line and providing a corresponding output logic signal to the CMOS circuit.

Abstract: A CMOS driver circuit which differentially drives a pair of transmission lines at a first terminal in response to a signal on the CMOS driver circuit's input terminal for reception of said signal at a second terminal is provided. The driver circuit has two pairs of drive transistors. Each drive transistor has first and second source/drains and a gate. Each drive transistor pair is connected to one of said transmission line pair, and has a NMOS transistor and a PMOS transistor.

Abstract: An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry.

Abstract: A driver circuit formed from CMOS material is provided for receiving an input logic signal from an internal CMOS circuit and inducing a corresponding output signal onto a terminated transmission line. The driver circuit comprises a pre-driver invertor having an input and an output. The invertor inverts a logic state of the input logic signal. The driver circuit also includes an output transistor that provides the output signal and has a drain electrically connected to the transmission line. The driver circuit also includes a control circuit for controlling the output signal during a transition of the input logic signal from a first logic state to a second logic state. The driver circuit is physically isolated from the internal CMOS circuit.

Abstract: An embodiment of the present invention is a customizable integrated circuit including a basic cell diffusion of four transistors in a substrate. A first metallization layer includes a plurality of connective strips that electrically connect to the basic cell by a plurality of contacts. A second metallization layer, after a first patterning and chemical etch, comprises an orthogonal matrix of conductors that are electrically connected to corresponding connective strips by a plurality of vias that are respectively positioned at an intersection of orthogonal conductors. A second patterning and chemical etch of the second metallization layer configures the basic cell according to a user's specification.

Abstract: A high-speed CMOS output buffer reduces transient current surges and provides high output DC drive. The buffer includes a first and a second CMOS inverter connected in parallel. Each of the two CMOS inverters includes an N channel and a P channel transistor. The gates of the transistors in the first inverter are controlled by a first control inverter having a first selected switching threshold voltage. The gate of the P channel transistor in the second inverter is controlled by a second control inverter having a switching threshold voltage higher than that of the first control inverter. The gate of the N channel transistor in the second inverter is controlled by a third control inverter having a switching threshold voltage lower than that of the first control inverter.

Abstract: A gate array is provided in which active areas within the substrate are arranged in alternating columns of opposite conductivity type and symmetrical about the center lines through each column so that CMOS devices can be advantageously formed by allocating only small increments of active area to metal routing. The substrate and well taps are also symmetrical about the column center line. The active area symmetry allows p-channel and n-channel transistors to be combined where the p-channel transistor is on either the right or left, thus increasing the flexibility in placing the elements within the integrated circuit chip.

Abstract: A CMOS driver circuit for integrated circuits capable of operating in two modes. The first, high speed, mode allows the driver circuit on an integrated circuit device to drive the internal signals of the device to the outside world for standard operation of the integrated circuit devices. The second mode causes the driver circuit to behave as a weak driver for easily testing the integrated circuit.

Abstract: A CMOS reset circuit has a reverse biased diode and a latch for latching a p-channel enhancement mode MOSFET on during the first part of the power-on cycle. The p-channel MOSFET is part of a voltage divider which also includes a resistor. When the voltage between p-channel MOSFET and resistor reach the threshold of an n-channel enhancement mode MOSFET, the p-channel MOSFET is switched off. Reset pulses are provided through one or two inverters by a load on the latch.