Abstract: A dual-output triple-Vdd charge pump as two pumped outputs that are both pumped to three times the power-supply voltage, 3×Vdd. This pumped output voltage is reduced by two p-channel inner diode drops, to 3×Vdd?2×|Vtp|. A pair of cross-coupled n-channel transistors alternately charge two inner nodes from the power supply. Inner pumping capacitors drive inner nodes between Vdd and 2×Vdd, and the cross-coupling of the gates turns off one of the cross-coupled n-channel transistors when its inner node is being driven high. A p-channel inner diode transistor connects an inner node to an outer node, causing a |Vtp| drop. The outer node is also pumped by an outer pumping capacitor that drives the outer node between 2×Vdd?|Vtp| and 3×Vdd?|Vtp|. A p-channel outer diode transistor conducts from the outer node to the pumped output node, causing another |Vtp| voltage drop. The pumped output voltage is maintained at 3×Vdd?2×|Vtp| by an output capacitor.

Abstract: A stable voltage that is independent of supply voltage is applied to a pair of current sources. A first current source generates a first current that passes through a first resistor, setting a compare-input voltage. A source-input voltage is applied to the first current source to vary the first current and the compare-input voltage. A second current source generates a stable current that passes through a second resistor, setting a reference voltage. The compare-input voltage and the reference voltage are applied to inputs of a comparator that generates an output voltage that indicates when the source-input voltage causes the compare-input voltage to rise past the reference voltage. The first and second currents track each other over temperature and process variations and are independent of supply voltage. A more accurate comparison of the source-input voltage is thus made.

Abstract: A stable voltage that is independent of supply voltage is applied to a pair of current sources. A first current source generates a first current that passes through a first resistor, setting a compare-in-put voltage. A source-input voltage is applied to the first current source to vary the first current and the compare-input voltage. A second current source generates a stable current that passes through a second resistor, setting a reference voltage. The compare-input voltage and the reference voltage are applied to inputs of a comparator that generates an output voltage that indicates when the source-input voltage causes the compare-input voltage to rise past the reference voltage. The first and second currents track each other over temperature and process variations and are independent of supply voltage. A more accurate comparison of the source-input voltage is thus made.

Abstract: A voltage booster drives the gate of a bus-switch n-channel transistor to a theoretical maximum of triple the power-supply voltage Vcc. The gate node is first driven to Vcc. Then the back-side of a first capacitor is driven from ground to Vcc, coupling a first voltage boost to the gate node. After a Schmidt-trigger detects the back-side of the first capacitor near Vcc, the back-side of a second capacitor is driven from ground to Vcc. The front-side of the second capacitor is connected to the back-side of the first capacitor. A second voltage boost is coupled across the first and second capacitors to increase the voltage boost of the gate node to near triple Vcc rather than just double Vcc.

Abstract: A fail-safe circuit for a differential receiver can tolerate noise. A latch is enabled when both differential inputs V+, V− rise above a reference voltage that is close to Vcc. The latch, once enabled, is set by an offset amplifier, signaling the fail-safe condition. The offset amplifier sets the latch when V+ is above or equal to V−. The differential amplifier has a small offset voltage to allow the latch to remain set when V+ and V− are equal in voltage. An output from a differential amplifier receiving V+ and V− can be blocked by a gate when the fail-safe condition is latched. Pullup resistors pull V+, V− to Vcc when an open failure occurs. The latch remains set when common-mode noise occurs on V+, V−, preventing noise from prematurely disabling the fail-safe condition. Such noise coupled into a broken cable is usually common-mode.

Abstract: An active terminating circuit has buffers to produce wider voltage drives on clamping transistors. A transmission line drives coupling capacitors. One capacitor drives an upper node that drives the gate of an upper buffer transistor. The upper buffer transistor drives a p-gate node coupled to a gate of a p-channel clamping transistor. The other capacitor drives a lower node that drives the gate of a lower buffer transistor, which drives an n-gate node of an n-channel clamping transistor. The drains of the clamping transistors are connected to the transmission line. Resistors pull the lower node to the power-supply voltage and pull the upper node to ground when no transitions occur on the transmission line, achieving zero standby power. When a transition is detected, it is coupled through the capacitors and buffered to the p-gate and n-gate nodes. Limiting transistors limit upper and lower node swings.

Abstract: An active terminating circuit has n-channel and p-channel sensing transistors with gates connected to a transmission line. The sensing transistors drive a back node connected to a pair of capacitors. One capacitor drives a p-gate node coupled to a gate of a p-channel clamping transistor, while the other capacitor drives an n-gate node coupled to a gate of an n-channel clamping transistor. The drains of the clamping transistors are connected to the transmission line. Resistors pull the p-gate node to the power-supply voltage and pull the n-gate node to ground when no transitions occur on the transmission line to achieve zero standby power. When a transition is detected, it is inverted and coupled through the capacitors to the p-gate and n-gate nodes. The p-channel clamping transistor is turned on for rising transitions, while the n-channel clamping transistor is turned on for falling transitions. Limiting transistors limit gate-node swings.

Abstract: A fail-safe circuit for a differential receiver can tolerate high common-mode voltages. An output from a differential amplifier that receives a V+ and a V− differential signal can be blocked by a NOR gate when the fail-safe condition is detected, such as when the V+, V− lines are open. Pullup resistors pull V+, V− to Vcc when an open failure occurs. A pair of comparators receive a reference voltage on the non-inverting input. Once comparator outputs a high when the V+ line is above the reference voltage, and the other comparator outputs a high when the V− line is above the reference voltage. When both V+ and V− are above the reference voltage, the NOR gate blocks the output from the differential amplifier, providing a fail-safe. Since the reference voltage is very close to Vcc, a high common-mode bias can exist on V+, V− without falsely activating the fail-safe circuit.

Abstract: A low-voltage differential signaling (LVDS) output buffer has an improved eye pattern. The LVDS buffer has two parallel stages. A primary stage generates enough current to generate a first voltage drop across a load resistor. At higher frequencies, parasitic capacitive coupling reduces this first voltage drop, closing the eye pattern. A boost stage generates an additional boost current through the load resistor, adding to the voltage drop and opening the eye pattern. The boost stage is coupled to the outputs by link transistors that are enabled by a pre-emphasis signal generated by resetable pulse generators. When outputs switch, the pre-emphasis signal pulses the link transistors on, adding the boost current. At high frequencies, the pulse generators are reset before the pre-emphasis signal ends. The boost current is continuously added at high frequencies, but at low frequencies the boost current only occurs during the pre-emphasis period after outputs switch.

Abstract: An amplifier designed from CMOS transistors provides a high current output, despite having a unity-gain configuration. A push-pull output stage drives the output using a p-channel pull-up transistor and an n-channel pull-down transistor. The pull-down transistor's gate is driven by an output from an inverting differential amplifier, that has one differential transistor gate driven by an input voltage and the other driven by the output voltage. A second differential amplifier is configured as a non-inverting differential amplifier, with one differential transistor gate driven by the input voltage and the other driven by the output voltage. The second differential amplifier drives an n-channel gate of an inverting stage, and the output of the inverting stage drives the p-channel pull-up transistor's gate.

Abstract: A gate-array cell uses smaller and larger transistors. Four larger transistors are provided: two n-channel and two p-channel. A small p-channel transistor is placed between the contact tabs of the polysilicon lines of the two larger p-channel transistors, and between the p-channel transistors and a N-well tap. A small n-channel transistor is similarly placed between the contact tabs of polysilicon lines of the two larger n-channel transistors, and between the n-channel transistors and a P-well tap. The cell is slightly expanded in height to accommodate the two smaller transistors. The smaller transistors enable a reduction in the number of transistors required for latches and flip-flops. The smaller transistors allow a feedback inverter to directly connect to an input, since the input can easily over-power the feedback current. This is not possible for standard gate array cells having only one transistor size. Transmission gates are eliminated when direct feedback is feasible.

Abstract: An n-channel bus switch has a transistor gate boosted above the power supply (Vcc) to increase current drive and reduce the channel resistance of the bus switch. No pulse generator is needed. The gate terminal is connected to a boosted node. When the bus switch is turned on, a pullup transistor drives the boosted node from ground to Vcc. The pulse generator is eliminated by using a Schmidt-trigger to sense the voltage of the boosted node. Once the Schmidt-trigger senses that the voltage of the boosted node is near Vcc, the pull-up is turned off. A delay line first drives the gate of the pullup transistor to a threshold below Vcc using an n-channel pullup, and then drives the gate to Vpp using a p-channel pullup. A delay line then drives the back-side of a capacitor from ground to Vcc. This voltage swing is coupled through the capacitor to the boosted node, driving the boosted node about 1.3 volts above Vcc. A small keeper transistor supplies a small current to the boosted node to counteract any leakage.

Abstract: A bus switch is constructed from an n-channel transistor. The gate terminal of the n-channel transistor is boosted above the power supply (Vcc) to increase current drive and reduce the channel resistance of the bus switch. The gate terminal is connected to a boosted node. When the bus switch is turned on, a pulse is generated to drive the boosted node from ground to Vcc. The boosted node is also an input of a delay line. After a delay through the delay line, the pulsed pull-up is turned off. Feeding the boosted node to the delay line allows the pulse to be self-timed. The delay line then drives the back-side of a capacitor from ground to Vcc. This voltage swing is coupled through the capacitor to the boosted node, driving the boosted node about 1.3 volts above Vcc. A small keeper transistor supplies a small current to the boosted node to counteract any leakage. This leaker transistor is connected to a charge pump, and the delay line that enables this keeper transistor is also connected to the charge pump.

Abstract: A synchronizer that has reduced latency is used for synchronizing and conditioning a clock-enable signal to a free-running clock. Once the clock-enable signal is synchronized it is used to enable and disable gating of the free-running clock to a gated clock that suspends pulsing in response to the clock-enable signal. A first-stage flip-flop is `meta-stable hardened` to reduce the probability of it becoming meta-stable. Gating on the clock and the clear inputs reduces the chance that simultaneous inputs will violate the timing of the flip-flop and thus cause metastability. A clear pulse is generated to clear the flip-flop. The clear pulse skews the flip-flop to be more likely to become metastable for one edge of the asynchronous input than for the other edge. The settling time to the second stage flip-flop is then adjusted to account for this skew in metastability. Settling time in the second stage is increased for the edge that is more likely to become metastable.

Abstract: An electronic system such as a Single-Chip-Module (SCM), a Multi-Chip-Module (MCM), or a Board-Level-Product (BLP) includes a plurality of units which are interconnected by a terminated transmission bus line. Each unit includes a CMOS circuit, a terminated bus line for signal transmission, and a driver/receiver circuit which is spaced from the CMOS circuit on a substrate. A guard ring is formed around at least a part of the CMOS circuit which faces the driver/receiver circuit. The driver/receiver circuit includes a driver for receiving an input logic signal from the CMOS circuit and inducing a corresponding signal onto the bus line, and a receiver for receiving an output signal from the bus line and providing a corresponding output logic signal to the CMOS circuit.