Patents by Inventor Anthony Yi Sheng Sun
Anthony Yi Sheng Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9842792Abstract: A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. The, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.Type: GrantFiled: January 27, 2016Date of Patent: December 12, 2017Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Danny Retuta, Hien Boon Tan, Anthony Yi Sheng Sun, Mary Annie Cheong
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Publication number: 20160211196Abstract: A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. The, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.Type: ApplicationFiled: January 27, 2016Publication date: July 21, 2016Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Danny RETUTA, Hien Boon TAN, Anthony Yi Sheng SUN, Mary Annie CHEONG
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Patent number: 9281218Abstract: A method of manufacturing a lead frame includes providing an electrically conductive layer having a plurality of holes at a top surface. The plurality of holes form a structure of leads and a die pad on the electrically conductive layer. The plurality of holes are filled with a non-conductive material. Next; an electrically conductive foil is attached on the top surface of the electrically conductive layer and the non-conductive epoxy material. Then, the electrically conductive foil is etched to create a network of leads, die pad, bus lines, dam bars and tie lines, wherein the bus lines connect the leads to the dam bar, the dam bar is connected to the tie line and the tie line is connected to the die pad.Type: GrantFiled: August 29, 2007Date of Patent: March 8, 2016Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Danny Retuta, Hien Boon Tan, Anthony Yi Sheng Sun, Mary Annie Cheong
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Patent number: 8129222Abstract: An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.Type: GrantFiled: November 26, 2003Date of Patent: March 6, 2012Assignee: United Test and Assembly Test Center Ltd.Inventors: Hien Boon Tan, Anthony Yi Sheng Sun
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Patent number: 8115292Abstract: An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.Type: GrantFiled: October 23, 2009Date of Patent: February 14, 2012Assignee: United Test and Assembly Center Ltd.Inventors: Chin Hock Toh, Yao Huang Huang, Ravi Kanth Kolan, Wei Liang Yuan, Susanto Tanary, Anthony Yi Sheng Sun
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Patent number: 8030768Abstract: A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections.Type: GrantFiled: April 24, 2008Date of Patent: October 4, 2011Assignee: United Test And Assembly Center Ltd.Inventors: Roel Robles, Danny Retuta, Mary Annie Cheong, Hien Boon Tan, Anthony Yi Sheng Sun, Richard Gan
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Patent number: 7948095Abstract: The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices. The methods may comprise a combination of wafer-level through silicon interconnect fabrication and wafer-level assembly processes.Type: GrantFiled: February 11, 2009Date of Patent: May 24, 2011Assignee: United Test and Assembly Center Ltd.Inventors: Catherine Bee Liang Ng, Chin Hock Toh, Anthony Yi-Sheng Sun
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Patent number: 7830006Abstract: A chip scale integrated circuit package includes an integrated circuit chip which has a first face and a second face. A plurality of pillar bumps are formed on the first face of the integrated circuit chip. An encapsulant material encapsulates the sides and the first face of the integrated circuit chip, and the pillar bumps. Upper ends of the pillar bumps remain free from encapsulant material and a substantially planar surface is formed by an upper surface of the encapsulant material and the upper ends of the pillar bumps. A plurality of solder balls are mounted on the substantially planar surface in locations corresponding to the upper ends of the pillar bumps.Type: GrantFiled: May 5, 2005Date of Patent: November 9, 2010Assignee: United Test and Assembly Center, Ltd.Inventors: Ravi Kanth Kolan, Hien Boon Tan, Anthony Yi Sheng Sun, Beng Kuan Lim, Krishnamoorthi Sivalingam
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Patent number: 7816775Abstract: A method for of manufacturing integrated circuit packages and a multi-chip integrated circuit package are disclosed. According to the method, a first die is attached onto a first side of a set of leads of a leadframe, and an adhesive is applied onto the set of leads at a second side opposite to the first side. A second die is attached onto the adhesive. The adhesive fills into the gaps defined by the set of leads. The adhesive is thereafter cured. In a multi-chip integrated circuit package made according to the method, the adhesive attaching the second die fills the gaps between the leads so that to avoid formation of internal cavities of the package.Type: GrantFiled: September 9, 2005Date of Patent: October 19, 2010Assignee: United Test and Assembly Center LimitedInventors: Chuen Khiang Wang, Hao Liu, Hien Boon Tan, Clifton Teik Lyk Law, Rahamat Bidin, Anthony Yi Sheng Sun
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Patent number: 7723833Abstract: A stacked die semiconductor package that includes a substrate with a plurality of adhesive portions arranged in a manner to create at least one gap between the adhesive portions. The package also includes a first semiconductor chip having a non-active surface in contact with the adhesive portions, and an active surface being electrically connected to the substrate. In the package, a second semiconductor chip the non-active surface of the second semiconductor chip is attached to the non-active surface of the first semiconductor chip by a layer of adhesive therebetween. The active surface of the second semiconductor chip is electrically connected to the substrate. An encapsulant material covers the first and second semiconductor chips and their associated electrical connections. The encapsulating material fills the at least one gap between the plurality of adhesive portions and thereby encapsulates the second semiconductor chip and its associated electrical connection.Type: GrantFiled: August 29, 2007Date of Patent: May 25, 2010Assignee: United Test and Assembly Center Ltd.Inventors: Gaurav Mehta, Hien Boon Tan, Susanto Tanary, Mary Annie Cheong, Anthony Yi Sheng Sun, Chuen Khiang Wang
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Publication number: 20100109169Abstract: A stiffener is provided for use in making semiconductor devices. The stiffener and method of use provided prevent or reduce warpage of a semiconductor package during the assembly process. More particularly, the stiffener functions to prevent or reduce warpage during molding of an assembly of wafers and/or dies. The stiffener may be positioned above the backside or non-active side of an assembly of wafer and/or dies during molding. The presence of the stiffener prevents or reduces warpage caused by CTE mismatch between the mold material and the wafer and/or under the high temperatures encountered in the process of molding. After molding, the stiffener may continue to provide support to the assembly.Type: ApplicationFiled: April 28, 2009Publication date: May 6, 2010Applicant: UNITED TEST AND ASSEMBLY CENTER LTDInventors: Ravi Kanth KOLAN, Anthony Yi-Sheng Sun, Chin Hock Toh, Catherine Bee Liang Ng, Xue Ren Zhang
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Patent number: 7678610Abstract: A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection.Type: GrantFiled: October 28, 2005Date of Patent: March 16, 2010Assignee: UTAC-United Test and Assembly Test Center Ltd.Inventors: Chuen Khiang Wang, Hien Boon Tan, Anthony Yi Sheng Sun, Sin Nee Song, Steven Yu Feng Yao, Hua Hong Tan
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Publication number: 20090200662Abstract: The present invention relates to semiconductor devices comprising two or more dies stacked vertically on top of one another, and methods of making the semiconductor devices. The methods may comprise a combination of wafer-level through silicon interconnect fabrication and wafer-level assembly processes.Type: ApplicationFiled: February 11, 2009Publication date: August 13, 2009Applicant: UNITED TEST AND ASSEMBLY CENTER LTDInventors: Catherine Bee Liang Ng, Chih Hock Toh, Anthony Yi-Sheng Sun
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Patent number: 7476569Abstract: A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with each other along an edge of the package. Also, the outer ends of the first leads form a first row along the edge of the package and the outer ends of the second leads form a second row along the edge of the package. In one embodiment, the first and second rows are parallel to each other and an encapsulant covers at least a portion of the first and second leads.Type: GrantFiled: May 2, 2008Date of Patent: January 13, 2009Assignee: United Test and Assembly Center Ltd.Inventors: Danny Vallejo Retuta, Hien Boon Tan, Susanto Tanary, Anthony Yi Sheng Sun, Soon Huat James Tan
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Publication number: 20080290509Abstract: A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.Type: ApplicationFiled: December 2, 2004Publication date: November 27, 2008Applicant: UNITED TEST AND ASSEMBLY CENTERInventors: Hien Boon Tan, Chuen Khiang Wang, Rahamat Bidin, Anthony Yi Sheng Sun, Desmond Yok Rue Chong, Ravi Kanth Kolan
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Publication number: 20080284015Abstract: A semiconductor package with a semiconductor chip having under bump metallizations (UBMs) on a first surface and a substrate having open vias. The substrate is attached to the semiconductor chip with the UBMs in alignment with the open vias. An encapsulant surrounds the semiconductor chip and the substrate and a conductor fills the open vias to form external package connections. A method of forming a semiconductor package having external package connections includes providing a semiconductor chip having under bump metallizations (UBMs) on a first surface; attaching the first surface of the semiconductor chip to a substrate, the UBMs of the semiconductor chip being in alignment with open vias formed in the substrate; encapsulating the semiconductor chip and the substrate; and filling with open vias with a conductor to form the external package connections.Type: ApplicationFiled: April 24, 2008Publication date: November 20, 2008Inventors: Roel Robles, Danny Retuta, Mary Annie Cheong, Hien Boon Tan, Anthony Yi Sheng Sun, Richard Gan
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Publication number: 20080251938Abstract: A semiconductor chip package and method of making the same. A first chip unit includes a first substrate and a first IC chip electrically connected to the first substrate. A second chip unit includes a second substrate and a second IC chip electronically connected to the second substrate. An adhesive material is provided on a surface of the first IC chip and the second chip unit is mounted onto the surface of the first chip unit including the adhesive material so that at least a portion of the second structure is encapsulated by the adhesive material, thereby providing some encapsulation in the same step as mounting. The first chip unit and the second chip unit may be separated by a spacer which may also provide an electrical connection.Type: ApplicationFiled: April 7, 2008Publication date: October 16, 2008Inventors: Chuen Khiang Wang, Hien Boon Tan, Anthony Yi Sheng Sun, Sin Nee Song, Steven Yu Feng Yao, Hua Hong Tan
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Publication number: 20080199985Abstract: A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with each other along an edge of the package. Also, the outer ends of the first leads form a first row along the edge of the package and the outer ends of the second leads form a second row along the edge of the package. In one embodiment, the first and second rows are parallel to each other and an encapsulant covers at least a portion of the first and second leads.Type: ApplicationFiled: May 2, 2008Publication date: August 21, 2008Inventors: Danny Vallejo Retuta, Hien Boon Tan, Susanto Tanary, Anthony Yi Sheng Sun, Soon Huat James Tan
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Patent number: 7375416Abstract: A semiconductor package includes a plurality of first leads, each with a top outer portion removed from the lead and an outer end, and a plurality of second leads, each with a bottom outer portion removed from the lead and an outer end. The first and second leads alternate with each other along an edge of the package. Also, the outer ends of the first leads form a first row along the edge of the package and the outer ends of the second leads form a second row along the edge of the package. In one embodiment, the first and second rows are parallel to each other and an encapsulant covers at least a portion of the first and second leads.Type: GrantFiled: April 19, 2006Date of Patent: May 20, 2008Assignee: United Test and Assembly Center Ltd.Inventors: Danny Vallejo Retuta, Hien Boon Tan, Susanto Tanary, Anthony Yi Sheng Sun, Soon Huat James Tan
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Patent number: 7361995Abstract: A thermally enhanced ball grid array package is disclosed. The package includes a base layer element and a flip chip die mounted on the base layer element. The die has a first surface electrically coupled to the base layer element, a second surface opposite to the first surface, and lateral sides. A molding compound encapsulates the base layer element and the lateral sides of the die. A surface is formed of the second surface of the die and an upper surface of the molding compound. A material is disposed on the surface, and a heat spreader is mounted on the material.Type: GrantFiled: February 3, 2004Date of Patent: April 22, 2008Assignees: Xilinx, Inc., UTAC - United Test and Assembly Test Center Ltd.Inventors: Kim Yong Goh, Rahul Kapoor, Anthony Yi-Sheng Sun, Desmond Yok Rue Chong, Lan H. Hoang