Abstract: A digital signal is interleaved by delaying samples thereof by an integral number times a unit delay in accordance with a cyclically repeated delay pattern (AL91) . . . AL(M) Select lines (AL91) . . . AL(M)) of a memory (HAS) are cyclically activated (HAS) at a cycle rate equal to unit delay. During the activation of a select line, both data is written and read from the memory. The data written comprises a relevant bit of each sample to be delayed in an integral number of sample groups. Each sample group is associated with one delay pattern cycle. The data read (b(1,1,j)@a1 . . . b(1,M,j)@aM . . . b(k,1,j)@a1 . . . b(k,M,j)@aM) comprises a number of bits which is equal to the number of bits written. The bits are read in accordance with the delay pattern. Accordingly, the speed requirements imposed on the memory (MEM) are relatively lax.

Abstract: A DAB receiver in which a reduced time de-interleaving memory for storing metrics is used, but which still allows processing of DAB services which normally would exceed the storage capacity of the memory. This is achieved by varying the length of a stored metric, depending upon the storage capacity required, by varying the number of stored reliability bits in a metric. In this way, a trade-off can be made between storage capacity and processing quality.

Abstract: In a digital audio broadcast receiver a digital audio transmission signal is supplied to a demodulator which provides demodulation samples. The demodulation samples are de-interleaved in a first section of a de-interleaving memory. After having been de-interleaved, demodulation samples are transferred to a second section of the de-interleaving memory. This transfer is effectuated in bursts via a relatively small buffer which stores the bursts. The second section of the de-interleaving memory effectively constitutes a relatively large buffer. De-interleaved demodulations samples are regularly read from the second section and supplied as a regular stream to a Viterbi decoder by means of a relatively small first-in first-out register.

Abstract: A data processor of modular architecture comprises a plurality of operation units, each serving to implement specific functionalities as required by the instruction set that determines the processor's operation. Register files for several ones among the operation units are merged. At least one of the register files is exclusively assigned to one of the operation units. At the expense of only a marginal increase, if any, of the number of instruction cycles, smaller register file areas in an IC embodiment, less register file control circuitry and simpler microcode words are obtained.

Abstract: A buffer memory device comprising memory locations for successively storing successive groups of data units, the successive groups being presented during successive phases, the data units in each group having different buffer periods which are recurrent for all groups. A modulo address generator generates, for each group of data units, a series of addresses for selected locations in a memory wherein the data units will be stored, there being logic address intervals between the successive addresses in the relevant series which correspond to the buffer periods of the respective data units. In every two successive series the memory addresses are shifted by one address interval unit with respect to each other. An efficient data occupation of the memory can thus be realized with simple addressing, since the write addresses during any phase can be used as the read addresses for already stored data units. The buffer device can be used as an interleaver or de interleaver for error correction in CD apparatus.

Abstract: A programmable logic unit performs only monadic, dyadic logic bit level, rather than arithmetic, operations in order to achieve high speed. The unit is formed of section for each output bit position. Each section includes a general function block which simultaneously performs as desired, one or more of the operations cntl1.A.B, cntl2.A.B, cntl3.A.B and cntl4.A.B, wherein A, A, B, B and cntl1 to cntl4 are logic signals and control signals respectively. The inputs of the general function block are connected to a data distribution bus via a multiplex circuit. This connection between the multiplex inputs and the distribution bus can be selected as desired (once), so that the number of different logic operations that can be selected is very large.