Abstract: An apparatus to insure safe behavior in an inverter system. In one embodiment, the apparatus includes a first high side gate driver, a first low side gate driver, a microcontroller configured to control the first high side and low side gate drivers. A voltage regulator provides a supply voltage to the microcontroller. A first pair of high side voltage regulators provide a first pair of high side supply voltages to the first high side gate driver. A first pair of low side voltage regulators provide a first pair of low side supply voltages to the first low side gate driver.

Abstract: One example discloses a power controller configured to modulate a load current sent to a load, including: a first chip including a set of higher-power circuits configured to directly modulate the load current sent to the load; a second chip electrically coupled to the first chip and including a set of lower-power circuits; wherein the set of higher-power circuits are electrically isolated from the set of lower-power circuits; a power control path distributed between the first chip and the second chip, and configured to modulate the load current sent to the load; a diagnostics path distributed between the first chip and the second chip, and configured to monitor the higher-power circuits in the first chip and the lower-power circuits in the second chip for a set of fault conditions; wherein a portion of the diagnostics path in the second chip includes a plausibility circuit configured to compare a load current commanded by a first portion of the power control path in the second chip to the load current sent to

Abstract: An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.

Abstract: An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.

Abstract: A dynamic safe state control circuit is disclosed that controls an electrical motor based on vehicle speed. A microcontroller or other processing device is configured to control an inverter system of an electrical motor. The dynamic safe state control circuit is configured to receive a first signal that corresponds to a speed of the electric motor. The circuit is configured to activate any one of a plurality of safe states in the inverter system based on the first signal and in response to a malfunction in the microcontroller.

Abstract: An apparatus is disclosed that in one embodiment includes a circuit configured to selectively activate a transistor. The circuit is further configured to assert a signal when the circuit detects an electrical short between terminals of the transistor or when the circuit detects the transistor does not conduct current while the transistor is activated by the circuit. The circuit is further configured to output another signal, which is set to a first state or a second state. The other signal is set to the first state when the circuit detects the electrical short. The other signal is set to the second state when the circuit detects the transistor does not conduct current while activated.

Abstract: In a battery management system, during a pre-charge mode, a first contactor is closed to provide a pre-charge current path from a low voltage battery supply node through a DCDC converter and through the first contactor to pre-charge a capacitor of an inverter for an electric motor. During a drive mode following the pre-charge mode, the first contactor is opened and a second contactor is closed to provide a drive mode current path from a high voltage battery supply node through the second contactor to the inverter to power the electric motor. In response to detecting an open fault in the second contactor during the drive mode, a limp mode is entered. During the limp mode, the first contactor is closed to provide a limp mode current path from the high voltage battery supply node through the first contactor to the inverter to power the electric motor.

Abstract: An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.

Abstract: An apparatus to insure safe behavior in an inverter system. In one embodiment, the apparatus includes a first high side gate driver, a first low side gate driver, a microcontroller configured to control the first high side and low side gate drivers. A voltage regulator provides a supply voltage to the microcontroller. A first pair of high side voltage regulators provide a first pair of high side supply voltages to the first high side gate driver. A first pair of low side voltage regulators provide a first pair of low side supply voltages to the first low side gate driver.

Abstract: A dynamic safe state control circuit is disclosed that controls an electrical motor based on vehicle speed. A microcontroller or other processing device is configured to control an inverter system of an electrical motor. The dynamic safe state control circuit is configured to receive a first signal that corresponds to a speed of the electric motor. The circuit is configured to activate any one of a plurality of safe states in the inverter system based on the first signal and in response to a malfunction in the microcontroller.

Abstract: An apparatus is disclosed that in one embodiment includes a circuit configured to selectively activate a transistor. The circuit is further configured to assert a signal when the circuit detects an electrical short between terminals of the transistor or when the circuit detects the transistor does not conduct current while the transistor is activated by the circuit. The circuit is further configured to output another signal, which is set to a first state or a second state. The other signal is set to the first state when the circuit detects the electrical short. The other signal is set to the second state when the circuit detects the transistor does not conduct current while activated.

Abstract: A system includes a power transistor having a first drain connected to a load, a first gate connected to a gate driver, wherein the gate driver is configured to drive a first gate voltage on the first gate, and a first source connected to a ground. A sampling transistor includes a second drain connected to the first gate, a second gate connected to the first drain and a second source. A sampling capacitor is connected between the second source and the ground, wherein the sampling transistor is configured to sample a Miller plateau voltage of the first gate voltage on the sampling capacitor, in response to the first gate voltage increasing to the Miller plateau voltage and a first drain voltage of the first drain decreasing to a value equal to the Miller plateau voltage plus a threshold voltage of the sampling transistor.

Abstract: A system includes a power transistor having a first drain connected to a load, a first gate connected to a gate driver, wherein the gate driver is configured to drive a first gate voltage on the first gate, and a first source connected to a ground. A sampling transistor includes a second drain connected to the first gate, a second gate connected to the first drain and a second source. A sampling capacitor is connected between the second source and the ground, wherein the sampling transistor is configured to sample a Miller plateau voltage of the first gate voltage on the sampling capacitor, in response to the first gate voltage increasing to the Miller plateau voltage and a first drain voltage of the first drain decreasing to a value equal to the Miller plateau voltage plus a threshold voltage of the sampling transistor.