Abstract: Systems and methods are disclosed for open block stability scanning. When a solid state memory block remains in an open state, where the block is only partially filled with written data, for a prolonged period of time, a circuit may perform a scan on the block to determine the stability of the stored data. When the scan indicates that the data is below a stability threshold, the data may be refreshed by reading the data and writing it to a new location. When the scan indicates that the data is above a stability threshold, the circuit may extend the time period in which the block may remain in the open state.

Abstract: Systems and methods for improving data refresh in flash memory are described. In one embodiment, the method includes identifying a first garbage collection unit (GCU) of the storage system, computing a parity function in relation to the first GCU, identifying a data impairment in a first block, the first block being from the N blocks in the first GCU, removing the first block from the first GCU after identifying the data impairment in the first block, and recomputing the parity function when the first block is not cloned.

Abstract: A memory device may include a memory unit having multiple channel structures connected to a common source and drain in parallel. The memory unit can include floating gate structures including control gates connected to word lines and charge trap layers to store charge to form tiered floating gate memory cells. In some embodiments, rows and columns of memory units can be connected to form a three dimensional memory device. A method of fabricating a memory unit having tiered channel structures utilizing common source and drain elements and 3D memory device utilizing rows and columns of memory units having multiple channel structures connected to the common source and drain elements in parallel is disclosed.

Abstract: Method and apparatus for managing a solid state memory, such as but not limited to a NAND flash memory. In some embodiments, a storage device includes a non-volatile solid state memory and a control circuit configured to transfer user data between the memory and a host device. The control circuit maintains, in a local memory, a data structure indicative of measured readback error rates associated with memory locations in the memory in relation to erasure counts associated with the memory locations. The control circuit retires a subset of the memory locations identified by the data structure from further availability to store user data from the host device responsive to the measured readback error rates, and responsive to the erasure counts of said memory locations indicating the memory has reached an end of life (EOL) condition.

Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.

Abstract: Systems and methods for low latency acquisition of soft data from a memory cell based on a sensing time and/or a leakage current are described. In one embodiment, the systems and methods may include applying a first read voltage to a word line of a page of memory cells selected by a processor of a flash memory device for a read operation, applying a pass voltage to word lines associated with one or more different pages of memory cells of the memory block, upon applying the first read voltage sensing whether a bit line of a memory cell in the selected page conducts, measuring a side effect associated with sensing whether the bit line of the memory cell in the selected page conducts, and assigning a LLR value to the memory cell as a soft LDPC input based at least in part on the measured side effect.

Abstract: Systems and methods for low latency acquisition of soft data from a memory cell based on a sensing time and/or a leakage current are described. In one embodiment, the systems and methods may include applying a first read voltage to a word line of a page of memory cells selected by a processor of a flash memory device for a read operation, applying a pass voltage to word lines associated with one or more different pages of memory cells of the memory block, upon applying the first read voltage sensing whether a bit line of a memory cell in the selected page conducts, measuring a side effect associated with sensing whether the bit line of the memory cell in the selected page conducts, and assigning a LLR value to the memory cell as a soft LDPC input based at least in part on the measured side effect.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a block of solid-state non-volatile memory cells are each programmed to an associated programmed state responsive to a respective amount of accumulated charge. A charge loss compensation circuit adds a relatively small amount of additional charge to the respective amount of accumulated charge in each of the memory cells to maintain the associated programmed states of the cells.

Abstract: An apparatus includes a controller capable of being coupled to a host interface and a memory device. The memory device includes two or more non-hierarchical, non-volatile memory units having different minimum addressable data unit sizes. The controller is configured to at least perform determining a workload indicator of a data object being stored in the memory device via the host interface. The controller selects one of the memory units in response to the workload indicator of the data object corresponding to the minimum addressable data unit size of the selected memory unit corresponding to the workload indicator. The data object is stored in the selected memory unit in response thereto.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a block of solid-state non-volatile memory cells are each programmed to an associated programmed state responsive to a respective amount of accumulated charge. A charge loss compensation circuit adds a relatively small amount of additional charge to the respective amount of accumulated charge in each of the memory cells to maintain the associated programmed states of the cells.

Abstract: An apparatus comprises a mass storage unit and a plurality of circuit modules including a machine learning module, a programmable state machine module, and input/output interfaces. Switching circuitry is configured to selectively couple the circuit modules. Configuration circuitry is configured to access configuration data from the mass storage unit and to operate the switching circuitry to connect the circuit modules according to the configuration data.

Abstract: Methods and systems that include receiving data to be written to a NAND array in a controller; and writing the data to the NAND array, the NAND array including both type A NAND cells and type B NAND cells, wherein the type A NAND cells and the type B NAND cells have at least one structural difference.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, data are written to a set of solid-state non-volatile memory cells so that each memory cell in the set is written to an associated initial programmed state. Drift in the programmed state of a selected memory cell in the set is detected, and the selected memory cell is partially reprogrammed to return the selected memory cell to the associated initial programmed state.

Abstract: Two or more workload indicators affecting a memory cell of a resistance-based, non-volatile memory are measured. The two or more workload indicators are applied to a transfer function that predicts a resistance shift and/or resistance noise variance in response to the two or more workload indicators. A result of the transfer function is applied to shift and/or determine a threshold resistance used for at least one of a program operation and a read operation affecting the memory cell. An error rate of the memory cell is reduced as a result.

Abstract: A connection between a user device and a network server is established. Via the connection, a deep learning network is formed for a processing task. A first portion of the deep learning network operates on the user device and a second portion of the deep learning network operates on the network server.

Abstract: First and second data representation are stored in first and second blocks of a non-volatile, solid-state memory. The first and second blocks share series-connected bit lines. The first and second blocks are selected and other blocks of the non-volatile, solid-state memory that share the bit lines are deselected. The bit lines are read to determine a combination of the first and second data representations. The combination may include a union or an intersection.

Abstract: Apparatus and method for managing data in a memory, such as but not limited to a flash memory array. In some embodiments, an apparatus includes an array of memory cells and a dual polarity charge pump. The dual polarity charge pump has a positive polarity voltage source which applies a positive voltage to a charge storage device to program a selected memory cell to a first programming state, and a negative polarity voltage source which applies a negative voltage to the charge storage device to program the selected memory cell to a different, second programming state.

Abstract: Memory arrays that include a first memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate; and a second memory cell having a channel; a first insulator; a floating gate; a second insulator; and a control gate, wherein the first insulator is positioned between the channel and the floating gate, the second insulator is positioned between the floating gate and the control gate, wherein the first memory cell and the second memory cell are positioned parallel to each other.

Abstract: A system includes a plurality of nonvolatile memory cells and a map that assigns connections between nodes of a neural network to the memory cells. Memory devices containing nonvolatile memory cells and applicable circuitry for reading and writing may operate with the map. Information stored in the memory cells can represent weights of the connections. One or more neural processors can be present and configured to implement the neural network.

Abstract: Methods and systems that include receiving data to be written to a NAND array in a controller; and writing the data to the NAND array, the NAND array including both type A NAND cells and type B NAND cells, wherein the type A NAND cells and the type B NAND cells have at least one structural difference.