Patents by Inventor Antoine Laures

Antoine Laures has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4491805
    Abstract: The invention relates to a device for regenerating a carrier wave from a BPSK or QPSK modulation signal. The device multiplies the received signal by two or four depending on whether it has a BPSK or QPSK modulation. The multiplication delivers a reference signal. The device also has a locked loop comprising a voltage-controlled oscillator. A frequency divider is connected between the oscillator output and a second input of a comparator, the output of which is connected to the control input of the oscillator. The central frequency of the oscillator is equal to three times the nominal frequency f.sub.o of the received modulated signal. The output of the oscillator is connected to one input of a mixer having another input which receives the reference signal and the output of which is connected to the first input of the phase comparator. The frequency divider divides by three to deliver the regenerated carrier wave. Identical band-pass filters have a central frequency equal to f.sub.
    Type: Grant
    Filed: March 10, 1982
    Date of Patent: January 1, 1985
    Inventors: Antoine Laures, Leon Horbacio
  • Patent number: 4352093
    Abstract: High-speed, digital/analog converter using a logic circuit with coupled emitters comprising a first stage formed by logic gates having a plurality of inputs and one output and a second current amplification stage formed by the same number of transistors as there are logic gates, e.g. transistor having an emitter, a base and a collector, each case of a transistor of the second stage being connected to the output of a logic gate of the first stage, said logic circuit also having a first supply line and a voltage V.sub.cc1 and connected to all the collectors of the transistors of the amplification stage, a second supply line at voltage V.sub.cc2, which differs from the first and is connected to the logic gates of the first stage and a third supply line at a voltage V.sub.EE and connected to the two stages, wherein the converter comprises resistors connected to the emitters of transistors, resistor connected to the transistor of rank k having the value R/2.sup.
    Type: Grant
    Filed: December 19, 1980
    Date of Patent: September 28, 1982
    Inventor: Antoine Laures