Patents by Inventor Antoine Riviere
Antoine Riviere has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10760100Abstract: The present invention relates to a novel polypeptide having the enzymatic activity of reduction of NADP+ using electrons from reduced ferredoxin (Ferredoxin-NADP+ reductase activity), a polynucleotide having a nucleotide sequence encoding such polypeptide and uses thereof. The invention relates to the modulation of the Ferredoxin NADP+ reductase activity in a microorganism by varying the expression level of the polynucleotide coding for such polypeptide. The invention also relates to the production of commodity chemicals, especially ethanol, n-butanol, 1,3-propanediol, 1,2-propanediol, isopropanol and acetone by fermenting microorganisms wherein their Ferredoxin NADP+ reductase activity is modulated.Type: GrantFiled: July 22, 2016Date of Patent: September 1, 2020Assignees: Institut National des Sciences Appliquees, Centre National de la Recherche Scientifique (CNRS), Institut National de la Recherche AgronomiqueInventors: Philippe Soucaille, Isabelle Meynial-Salles, Céline Foulquier, Antoine Riviere
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Publication number: 20180216138Abstract: The present invention relates to a novel polypeptide having the enzymatic activity of reduction of NADP+ using electrons from reduced ferredoxin (Ferredoxin-NADP+ reductase activity), a polynucleotide having a nucleotide sequence encoding such polypeptide and uses thereof. The invention relates to the modulation of the Ferredoxin NADP+ reductase activity in a microorganism by varying the expression level of the polynucleotide coding for such polypeptide. The invention also relates to the production of commodity chemicals, especially ethanol, n-butanol, 1,3-propanediol, 1,2-propanediol, isopropanol and acetone by fermenting microorganisms wherein their Ferredoxin NADP+ reductase activity is modulated.Type: ApplicationFiled: July 22, 2016Publication date: August 2, 2018Applicants: Institut National des Sciences Appliquees, Centre National de la Recherche Scientifique (CNRS), Institut National de la Recherche AgronomiqueInventors: Philippe Soucaille, Isabelle Meynial-Salles, Céline Foulquier, Antoine Riviere
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Patent number: 8009396Abstract: A technique that minimizes false triggering of an electrostatic discharge (ESD) protection circuit is disclosed. In an embodiment, the resistor-capacitor (RC) time constant of an ESD trigger element is reduced during normal operation minimizing the risk of false triggering. Circuit layout area is saved without the need of a timeout circuit associated with releasing a device maintaining a trigger state (i.e., a trigger latch). A RC time constant for triggering is set in an operational context according to conditions of usage and desired application of the ESD protection circuit.Type: GrantFiled: February 13, 2008Date of Patent: August 30, 2011Assignee: Atmel Rousset S.A.S.Inventors: David Bernard, Jean-Jacques Kazazian, Antoine Riviere
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Patent number: 7990666Abstract: An electrostatic discharge protection circuit comprises a comparator coupled between a power supply terminal and ground. The comparator responds to an electrostatic discharge event producing a trigger signal at a comparator output. The comparator comprises a first and second current mirror. The first and second current mirrors each comprise a sense device and a mirror device. The mirror devices are coupled in series between the power supply terminal and ground. The first mirror device produces an incident current and the second mirror device receives an absorption current. With a supply voltage on the power supply terminal equal to or greater than a trigger supply voltage, the absorption current exceeds the incident current and produces a trigger signal at the comparator output. The trigger signal activates a shunt device that shunts current from the power supply terminal to ground.Type: GrantFiled: July 19, 2010Date of Patent: August 2, 2011Assignee: Atmel CorporationInventors: Antoine Riviere, Frederic Demolli, David Bernard
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Publication number: 20100277841Abstract: An electrostatic discharge protection circuit comprises a comparator coupled between a power supply terminal and ground. The comparator responds to an electrostatic discharge event producing a trigger signal at a comparator output. The comparator comprises a first and second current mirror. The first and second current mirrors each comprise a sense device and a mirror device. The mirror devices are coupled in series between the power supply terminal and ground. The first mirror device produces an incident current and the second mirror device receives an absorption current. With a supply voltage on the power supply terminal equal to or greater than a trigger supply voltage, the absorption current exceeds the incident current and produces a trigger signal at the comparator output. The trigger signal activates a shunt device that shunts current from the power supply terminal to ground.Type: ApplicationFiled: July 19, 2010Publication date: November 4, 2010Applicant: Atmel CorporationInventors: Antoine Riviere, Frederic Demolli, David Bernard
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Patent number: 7760476Abstract: An electrostatic discharge protection circuit comprises a comparator coupled between a power supply terminal and ground. The comparator responds to an electrostatic discharge event producing a trigger signal at a comparator output. The comparator comprises a first and second current mirror. The first and second current mirrors each comprise a sense device and a mirror device. The mirror devices are coupled in series between the power supply terminal and ground. The first mirror device produces an incident current and the second mirror device receives an absorption current. With a supply voltage on the power supply terminal equal to or greater than a trigger supply voltage, the absorption current exceeds the incident current and produces a trigger signal at the comparator output. The trigger signal activates a shunt device that shunts current from the power supply terminal to ground.Type: GrantFiled: June 7, 2007Date of Patent: July 20, 2010Assignee: Atmel CorporationInventors: Antoine Riviere, Frederic Demolli, David Bernard
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Publication number: 20090201615Abstract: A technique that minimizes false triggering of an electrostatic discharge (ESD) protection circuit is disclosed. In an embodiment, the resistor-capacitor (RC) time constant of an ESD trigger element is reduced during normal operation minimizing the risk of false triggering. Circuit layout area is saved without the need of a timeout circuit associated with releasing a device maintaining a trigger state (i.e., a trigger latch). A RC time constant for triggering is set in an operational context according to conditions of usage and desired application of the ESD protection circuit.Type: ApplicationFiled: February 13, 2008Publication date: August 13, 2009Applicant: ATMEL CORPORATIONInventors: David Bernard, Jean-Jacques Kazazian, Antoine Riviere
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Patent number: 7570468Abstract: An ESD protection circuit incorporates an ESD shunt device triggered by an ESD trigger network. In non-powered situations, a first RC time constant in the ESD trigger network, corresponds with the time range of the onset an ESD event and controls application of the ESD shunt device in response to the ESD event. A second RC time constant in a shunt trigger network is selected to be longer than the first RC time constant and holds-off triggering of a shunt device during ESD shunt protection. When activated during powered-on operation, the shunt device shunts a resistive element in the ESD trigger network forming a third time constant. The shunt device guards against false triggering during noise on a power rail by maintaining the third time constant in the ESD trigger network. The third time constant ensures that power rail voltage buildup due to noise dissipates before a false trigger develops.Type: GrantFiled: June 7, 2007Date of Patent: August 4, 2009Assignee: Atmel CorporationInventors: David Bernard, Antoine Riviere
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Publication number: 20080304191Abstract: An electrostatic discharge protection circuit comprises a comparator coupled between a power supply terminal and ground. The comparator responds to an electrostatic discharge event producing a trigger signal at a comparator output. The comparator comprises a first and second current mirror. The first and second current mirrors each comprise a sense device and a mirror device. The mirror devices are coupled in series between the power supply terminal and ground. The first mirror device produces an incident current and the second mirror device receives an absorption current. With a supply voltage on the power supply terminal equal to or greater than a trigger supply voltage, the absorption current exceeds the incident current and produces a trigger signal at the comparator output. The trigger signal activates a shunt device that shunts current from the power supply terminal to ground.Type: ApplicationFiled: June 7, 2007Publication date: December 11, 2008Applicant: ATMEL CORPORATIONInventors: Antoine Riviere, Frederic Demolli, David Bernard
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Publication number: 20080007882Abstract: An ESD protection circuit incorporates an ESD shunt device triggered by an ESD trigger network. In non-powered situations, a first RC time constant in the ESD trigger network, corresponds with the time range of the onset an ESD event and controls application of the ESD shunt device in response to the ESD event. A second RC time constant in a shunt trigger network is selected to be longer than the first RC time constant and holds-off triggering of a shunt device during ESD shunt protection. When activated during powered-on operation, the shunt device shunts a resistive element in the ESD trigger network forming a third time constant. The shunt device guards against false triggering during noise on a power rail by maintaining the third time constant in the ESD trigger network. The third time constant ensures that power rail voltage buildup due to noise dissipates before a false trigger develops.Type: ApplicationFiled: June 7, 2007Publication date: January 10, 2008Applicant: ATMEL CORPORATIONInventors: David Bernard, Antoine Riviere