Patents by Inventor Anton Chernoff

Anton Chernoff has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9658895
    Abstract: The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes providing a user interface comprising selectable boot-time configuration data and selecting, based on at least one user selection of the boot-time configuration data, a boot-time configuration for at least one node of a cluster of nodes of the computing system. The method further includes configuring the at least one node of the cluster of nodes with the selected boot-time configuration to modify at least one boot-time parameter of the at least one node.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: May 23, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Keith A. Lowery, Patryk Kaminski, Anton Chernoff
  • Patent number: 9372773
    Abstract: A processor, a method and a computer-readable medium for recording branch addresses are provided. The processor comprises hardware registers and first and second circuitry. The first circuitry is configured to store a first address associated with a branch instruction in the hardware registers. The first circuitry is further configured to store a second address that indicates where the processor execution is redirected to as a result of the branch instruction in the hardware registers. The second circuitry is configured to, in response to a second instruction, retrieve a value of at least one of the registers. The second instruction can be a user-level instruction.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: June 21, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph Lee Greathouse, Anton Chernoff
  • Patent number: 9262231
    Abstract: The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes determining, based on a shared execution of a workload by a cluster of nodes of the computing system, that at least one node of the cluster of nodes operated at less than a threshold operating capacity during the shared execution of the workload. The method further includes selecting a modified hardware configuration of the cluster of nodes based on the determining such that the cluster of nodes with the modified hardware configuration has at least one of a reduced computing capacity and a reduced storage capacity.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: February 16, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Keith A. Lowery, Patryk Kaminski, Anton Chernoff
  • Patent number: 9154451
    Abstract: Described are systems and methods for communication between a plurality of electronic devices and an aggregation device. An aggregation device processes instructions related to a configuration of an electronic device in communication with the aggregation device. One or more virtual devices are generated in response to processing the instructions. The electronic device enumerates a configuration space to determine devices for use by the electronic device. The aggregation device detects an access of the configuration space by the electronic device. The one or more virtual devices are presented from the aggregation device to the electronic device in accordance with the instructions.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 6, 2015
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Anton Chernoff, Venkata S. Krishnan, Mark Hummel, David E. Mayhew, Michael J. Osborn
  • Patent number: 9152532
    Abstract: The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes selecting, based on a user selection received via a user interface, a workload for execution on a cluster of nodes of the computing system. The workload is selected from a plurality of available workloads including an actual workload and a synthetic test workload. The method further includes configuring the cluster of nodes of the computing system to execute the selected workload such that processing of the selected workload is distributed across the cluster of nodes. The synthetic test workload may be generated by a code synthesizer based on a set of user-defined workload parameters provided via a user interface that identify execution characteristics of the synthetic test workload.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: October 6, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Keith A. Lowery, Patryk Kaminski, Anton Chernoff
  • Publication number: 20150106574
    Abstract: The described embodiments include a computing device that comprises at least one memory die having memory circuits and memory die processing circuits, and a logic die coupled to the at least one memory die, the logic die having logic die processing circuits. In the described embodiments, the memory die processing circuits are configured to perform memory die processing operations on data retrieved from or destined for the memory circuits and the logic die processing circuits are configured to perform logic die processing operations on data retrieved from or destined for the memory circuits.
    Type: Application
    Filed: October 15, 2013
    Publication date: April 16, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Nuwan S. Jayasena, Anton Chernoff
  • Patent number: 8929220
    Abstract: In a processing system comprising a plurality of processing nodes coupled via a switching fabric, a method includes implementing a flow control property for a data flow in the switching fabric based on an addressing property of an address of a virtual network interface controller associated with the data flow. A switching fabric includes a plurality of ports, each port coupleable to a corresponding processing node, and switching logic coupled to the plurality of ports. The switching fabric further includes flow control logic to implement a flow control property for a data flow in the switching logic based on an addressing property of an address of a virtual network interface controller associated with the data flow.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: January 6, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Jr., Anton Chernoff, Mark D. Hummel
  • Publication number: 20140372734
    Abstract: A processor, a method and a computer-readable medium for recording branch addresses are provided. The processor comprises hardware registers and first and second circuitry. The first circuitry is configured to store a first address associated with a branch instruction in the hardware registers. The first circuitry is further configured to store a second address that indicates where the processor execution is redirected to as a result of the branch instruction in the hardware registers. The second circuitry is configured to, in response to a second instruction, retrieve a value of at least one of the registers. The second instruction can be a user-level instruction.
    Type: Application
    Filed: June 12, 2013
    Publication date: December 18, 2014
    Inventors: Joseph Lee Greathouse, Anton Chernoff
  • Patent number: 8887056
    Abstract: The present disclosure relates to a method, system, and apparatus for configuring a computing system, such as a cloud computing system. A method includes, based on user selections received via a user interface, configuring a cluster of nodes by selecting the cluster of nodes from a plurality of available nodes, selecting a workload container module from a plurality of available workload container modules for operation on each node of the selected cluster of nodes, and selecting a workload for execution with the workload container on the cluster of nodes. Each node of the cluster of nodes includes at least one processing device and memory, and the cluster of nodes is operative to share processing of a workload.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: November 11, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Keith A. Lowery, Patryk Kaminski, Anton Chernoff
  • Publication number: 20140258688
    Abstract: Methods and systems are provided for generating a benchmark representative of a reference process. One method involves obtaining execution information for a subset of the plurality of instructions of the reference process from a pipeline of a processing module during execution of those instructions by the processing module, determining performance characteristics quantifying the execution behavior of the reference process based on the execution information, and generating the benchmark process that mimics the quantified execution behavior of the reference process based on the performance characteristics.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Mauricio Breternitz, Anton Chernoff, Keith A. Lowery
  • Patent number: 8806025
    Abstract: Described is an aggregation device comprising a plurality of virtual network interface cards (vNICs) and an input/output (I/O) processing complex. The vNICs are in communication with a plurality of processing devices. Each processing device has at least one virtual machine (VM). The I/O processing complex is between the vNICs and at least one physical NIC. The I/O processing complex includes at least one proxy NIC and a virtual switch. The virtual switch exchanges data with a processing device of the plurality of processing devices via a communication path established by a vNIC of the plurality of vNICs between the at least one VM and at least one proxy NIC.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: August 12, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark Hummel, David E. Mayhew, Michael J. Osborn, Anton Chernoff, Venkata S. Krishnan
  • Patent number: 8788794
    Abstract: A processing core in a multi-processing core system is configured to execute a sequence of instructions as a single atomic memory transaction. The processing core validates that the sequence meets a set of one or more atomicity criteria, including that no instruction in the sequence instructs the processing core to access shared memory. After validating the sequence, the processing core executes the sequence as a single atomic memory transaction, such as by locking a source cache line that stores shared memory data, executing the validated sequence of instructions, storing a result of the sequence into the source cache line, and unlocking the source cache line.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: July 22, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin C. Serebrin, David A. Kaplan, Anton Chernoff
  • Patent number: 8782645
    Abstract: A system and method for efficient automatic scheduling of the execution of work units between multiple heterogeneous processor cores. A processing node includes a first processor core with a general-purpose micro-architecture and a second processor core with a single instruction multiple data micro-architecture. A computer program comprises one or more compute kernels, or function calls. A compiler computes pre-runtime information of the given function call. A runtime scheduler produces one or more work units by matching each of the one or more kernels with an associated record of data. The scheduler assigns work units either to the first or to the second processor core based at least in part on the computed pre-runtime information. In addition, the scheduler is able to change an original assignment for a waiting work unit based on dynamic runtime behavior of other work units corresponding to a same kernel as the waiting work unit.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: July 15, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Patryk Kaminski, Keith Lowery, Anton Chernoff
  • Patent number: 8752008
    Abstract: A sampling based DBR framework which leverages a separate core for program analysis. The framework includes a hardware performance monitor, a DBR service that executes as a separate process and a lightweight DBR agent that executes within a client process. The DBR service aggregates samples from the hardware performance monitor, performs region selection by deducing the program structure around hot samples, performs transformations on the selected regions (e.g. optimization), and generates replacement code. The DBR agent then patches the client process to use the replacement code.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: June 10, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark Herdeg, Steven T. Tye, Michael Bedy, Anton Chernoff
  • Patent number: 8683468
    Abstract: A system and method for automatically migrating the execution of work units between multiple heterogeneous cores. A computing system includes a first processor core with a single instruction multiple data micro-architecture and a second processor core with a general-purpose micro-architecture. A compiler predicts execution of a function call in a program migrates at a given location to a different processor core. The compiler creates a data structure to support moving live values associated with the execution of the function call at the given location. An operating system (OS) scheduler schedules at least code before the given location in program order to the first processor core. In response to receiving an indication that a condition for migration is satisfied, the OS scheduler moves the live values to a location indicated by the data structure for access by the second processor core and schedules code after the given location to the second processor core.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: March 25, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Patryk Kaminski, Keith Lowery, Anton Chernoff, Dz-Ching Ju
  • Publication number: 20140068088
    Abstract: Described are a system and method for processing a media access control (MAC) address. A communication is established between a processing device and a network port of a data switching device. The data switching device assigns a MAC address to the processing device. The assigned MAC address is directly associated with the network port of the data switching device absent a learning mechanism.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Venkata S. Krishnan, Anton Chernoff, Mark Hummel, David E. Mayhew
  • Publication number: 20140056141
    Abstract: In a processing system comprising a plurality of processing nodes coupled via a switching fabric, a method includes implementing a flow control property for a data flow in the switching fabric based on an addressing property of an address of a virtual network interface controller associated with the data flow. A switching fabric includes a plurality of ports, each port coupleable to a corresponding processing node, and switching logic coupled to the plurality of ports. The switching fabric further includes flow control logic to implement a flow control property for a data flow in the switching logic based on an addressing property of an address of a virtual network interface controller associated with the data flow.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, JR., Anton Chernoff, Mark D. Hummel
  • Publication number: 20140059160
    Abstract: Described are systems and methods for communication between a plurality of electronic devices and an aggregation device. An aggregation device processes instructions related to a configuration of an electronic device in communication with the aggregation device. One or more virtual devices are generated in response to processing the instructions. The electronic device enumerates a configuration space to determine devices for use by the electronic device. The aggregation device detects an access of the configuration space by the electronic device. The one or more virtual devices are presented from the aggregation device to the electronic device in accordance with the instructions.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Anton Chernoff, Venkata S. Krishnan, Mark Hummel, David E. Mayhew, Michael J. Osborn
  • Publication number: 20140047272
    Abstract: The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes selecting, based on a user selection received via a user interface, a workload for execution on a cluster of nodes of the computing system. The workload is selected from a plurality of available workloads including an actual workload and a synthetic test workload. The method further includes configuring the cluster of nodes of the computing system to execute the selected workload such that processing of the selected workload is distributed across the cluster of nodes. The synthetic test workload may be generated by a code synthesizer based on a set of user-defined workload parameters provided via a user interface that identify execution characteristics of the synthetic test workload.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 13, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Keith A. Lowery, Patryk Kaminski, Anton Chernoff
  • Publication number: 20140047342
    Abstract: The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes initiating a hardware performance assessment test on a group of available nodes to obtain actual hardware performance characteristics of the group of available nodes. The method further includes selecting a subset of nodes for the computing system from the group of available nodes based on a comparison of the actual hardware performance characteristics of the group of available nodes and desired hardware performance characteristics.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 13, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Keith A. Lowery, Patryk Kaminski, Anton Chernoff