Abstract: A work station which includes a central processing unit (CPU), first and second interface chips connected to respective external or peripheral units, and a local bus connected to the CPU and chips and adapted for multiple byte data communication between the CPU and chips. First and second one-byte registers are included in the first and second chips, respectively, and are simultaneously accessible by the CPU.

Abstract: An interface circuit and method for transferring data between first and second buses. The circuit includes a buffer having a plurality of registers and write and read means. The write means stores data words received from the second bus in non-sequential registers. The read means transfers the data words from sequential registers to the first bus.

Abstract: A DMA controller is connected to a CPU in a work station. The controller includes a multiple byte memory address register (MAR), and a pointer register connected between the CPU and MAR. The pointer register is responsive to a command from the CPU to give the CPU successive access to the byte positions of the MAR for writing a memory address thereto. The DMA controller may also include a single byte register associated with the pointer register and connected between the CPU and MAR. The CPU writes an address to the MAR one byte at a time via the single byte register. Preferably, the MAR has a capacity of four 8 bit bytes.

Abstract: An architecture and method for operating a work station. The work station includes a CPU, a bus interface unit and a control line. The CPU is selected from a group of CPUs differing in certain operational parameters. The bus interface circuit is connected between an external bus and the CPU. The control line is connected to the interface circuit and provides a signal indicating the type of CPU connected to the circuit.

Abstract: A method of configuring a plurality of work station units, in which the units share common addresses. The units are activated one at a time with the activated unit being given configuration data corresponding to the common addresses. In this manner, an unlimited number of units of a work station can be configured with a limited number of I/O addresses.

Abstract: A work station connected to an asynchronous bus for transferring a starting address and consecutive data elements. The work station includes a CPU and memory unit, and an interface circuit connected between the bus and CPU. It also includes synchronous bus connecting the interface circuit, CPU and memory unit, and a system clock defining consecutive time slots and connected to the circuit. The circuit controls the synchronous bus transfer of the address in a first time slot and consecutive data elements in consecutive time slots.

Abstract: A work station, including a central processing unit (CPU), first, second and third integrated circuit interface chips, connected to an external bus, memory and peripheral unit, respectively, and a local bus, coupled to the CPU and chips. Each chip includes an internal bus interconnecting operating units disposed therein. Each chip is adapted to operate at the same clock frequency as the CPU, but with operational signals generated on its respective internal bus independently of the CPU. The internal bus on the first chip includes a burst mode control line for selected operating units. An operating unit obtaining access to the internal bus and activating its burst mode control line is effective to lock the internal bus for a plurality of operating cycles, during which data is transferred continuously in a burst mode over the internal bus.

Abstract: A work station, including a central processing unit (CPU), first, second and third integrated circuit interface chips connected to an external bus, memory and peripheral unit, respectively, and a local bus connected to the CPU and interface chips. Each chip includes an internal bus interconnecting operating units disposed therein. Each interface chip is adapted to operate at the same clock frequency as the CPU, but with operational signals generated on its respective internal bus independently of the CPU.