Abstract: A device, system, and method performs an adaptive simulation. The method performed by a similar includes receiving a release to be incorporated into a user device, the user device being a deployed device. The method includes receiving a profile of the user device, the profile being indicative of settings and usage information of the user device. The method includes generating a simulated user device corresponding to the user device, the simulated user device having a simulated profile corresponding to the profile. The method includes performing, by the simulator, a simulation for the release based upon the simulated user device and the simulated profile.

Abstract: Embodiments of apparatus and methods for virtualized computing are described. In embodiments, an apparatus may include one of more processor cores and a cache coupled to the one or more processor cores. The apparatus may further include a hypervisor operated by the one or more processor cores to manage operation of virtual machines on the apparatus, including selecting a part of the cache to store selected data or code of the hypervisor or one of the virtual machines, and locking the part of the cache to prevent the selected data or code from being evicted from the cache. Other embodiments may be described and/or claimed.

Abstract: A device, system, and method performs an adaptive simulation. The method performed by a similar includes receiving a release to be incorporated into a user device, the user device being a deployed device. The method includes receiving a profile of the user device, the profile being indicative of settings and usage information of the user device. The method includes generating a simulated user device corresponding to the user device, the simulated user device having a simulated profile corresponding to the profile. The method includes performing, by the simulator, a simulation for the release based upon the simulated user device and the simulated profile.

Abstract: Systems and methods may provide for detecting a time critical code section associated with a real time processor core and suspending execution on a suspendable processor core in response to the time critical code section. Additionally, execution on the suspendable core may be resumed when the real time processor core reaches the end of the time critical code section. In one example, execution is suspended by issuing an inter-processor interrupt (IPI) from the real time core to the suspendable core, wherein execution may be resumed when the real time core conducts a write to a memory location that is monitored by the suspendable core during suspension of execution.

Abstract: Embodiments of apparatus and methods for virtualized computing are described. In embodiments, an apparatus may include one of more processor cores and a cache coupled to the one or more processor cores. The apparatus may further include a hypervisor operated by the one or more processor cores to manage operation of virtual machines on the apparatus, including selecting a part of the cache to store selected data or code of the hypervisor or one of the virtual machines, and locking the part of the cache to prevent the selected data or code from being evicted from the cache. Other embodiments may be described and/or claimed.

Abstract: Systems and methods may provide for detecting a time critical code section associated with a real time processor core and suspending execution on a suspendable processor core in response to the time critical code section. Additionally, execution on the suspendable core may be resumed when the real time processor core reaches the end of the time critical code section. In one example, execution is suspended by issuing an inter-processor interrupt (IPI) from the real time core to the suspendable core, wherein execution may be resumed when the real time core conducts a write to a memory location that is monitored by the suspendable core during suspension of execution.