Patents by Inventor Anton P. M. Van Arendonk

Anton P. M. Van Arendonk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090279575
    Abstract: A carrier substrate (100) with laser sources includes a transparent center substrate (20), an upper substrate (30) adhered to the center substrate having openings (40) formed therein to expose the center substrate on a first side, and a lower substrate (32) adhered to the center substrate on a second side opposite the first side and having openings (42) formed therein to expose the center substrate on the second side, the openings on the lower substrate corresponding to positions of the openings in the upper substrate. Frequency conversion elements (60) are disposed on the center substrate within the openings of the lower substrate. Laser dies (70) are aligned to the frequency conversion elements and coupled to the lower substrate to provide light though the frequency conversion elements and the center substrate during operation. Methods for fabrication are also disclosed.
    Type: Application
    Filed: December 13, 2006
    Publication date: November 12, 2009
    Applicant: Koninklijke Philips Electronics, N.V.
    Inventors: Eric C.E. van Grunsven, Willem Hoving, Anton P.M. van Arendonk, Johannes W. Weekamp, Olaf T.J. Vermeulen, Marc A. de Samber
  • Patent number: 4948459
    Abstract: A method of enabling electrical connection to a substructure (10) forming part of an electronic device, such as an integrated circuit, is described in which an aluminum-containing electrically conductive level (1) is provided on a surface (12) of the substructure (10), an insulating layer (2) is deposited so as to cover the aluminum-containing electrically conductive level (1), a photosensitive resist layer (3) is provided on the insulating layer and a plasma etching step is then used to etch away insulating material so as to expose an electrically conductive surface to enable electrical connection to be made to the level (1). The insulating material (2) may be etched through a window in the resist layer (3) so as to form a via (14) or the resist layer (3) and insulating material (2) may be etched uniformly to provide a planarized surface.
    Type: Grant
    Filed: January 4, 1989
    Date of Patent: August 14, 1990
    Assignee: U.S. Philips Corporation
    Inventors: Josephus M. F. G. van Laarhoven, Leendert de Bruin, Anton P. M. van Arendonk
  • Patent number: 4766089
    Abstract: A semiconductor device is set forth comprising a number of parallel first electrodes (1) which are located on an insulating layer and are mutually separated by grooves with insulated walls, in which second electrodes (2) coplanar with the first electrodes (1) are provided. According to the invention, the first electrodes (1) are covered by an insulating layer provided with first contact windows (7), which each overlap at least one second electrode (2). The second electrodes (2) are provided with self-aligned second contact windows (8). Each second electrode (2) exhibits between its second contact window (8) and the first contact windows (7) overlapping the second electrode and also between said first contact windows (7), at least one interruption (9).
    Type: Grant
    Filed: December 11, 1987
    Date of Patent: August 23, 1988
    Assignee: U.S. Philips Corporation
    Inventors: Geert J. T. Davids, Anton P. M. van Arendonk
  • Patent number: 4754311
    Abstract: A semiconductor device is set forth comprising a number of parallel first electrodes (1) which are located on an insulating layer and are mutually separated by grooves with insulated walls, in which second electrodes (2) coplanar with the first electrodes (1) are provided. According to the invention, the first electrodes (1) are covered by an insulating layer provided with first contact windows (7), which each overlap at least one second electrode (2). The second electrodes (2) are provided with self-aligned second contact windows (8). Each second electrode (2) exhibits between its second contact window (8) and the first contact windows (7) overlapping the second electrode and also between said first contact windows (7), at least one interruption (9).
    Type: Grant
    Filed: May 1, 1986
    Date of Patent: June 28, 1988
    Assignee: U.S. Philips Corp.
    Inventors: Geert J. T. Davids, Anton P. M. Van Arendonk
  • Patent number: 4698126
    Abstract: A method of manufacturing a semiconductor device, in which a double layer consisting of a layer of polycrystalline silicon and a top layer of a silicide is applied to a surface of a semiconductor substrate coated with a layer of silicon oxide. After an etching mask has been provided, the double layer is etched in a plasma formed in chlorine gas to which up to 20% by volume of tetrachloromethane is added until the layer of polycrystalline silicon is etched. Thus, the double layer is etched anisotropically and the layer of silicon oxide is attacked in practice to a very small extent.
    Type: Grant
    Filed: March 3, 1986
    Date of Patent: October 6, 1987
    Assignee: U.S. Philips Corporation
    Inventors: Alfred J. Van Roosmalen, Anton P. M. Van Arendonk