Patents by Inventor Anton Prueckl
Anton Prueckl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8698298Abstract: A laminate electronic device comprises a first semiconductor chip, the first semiconductor chip defining a first main face and a second main face opposite to the first main face, and having at least one electrode pad on the first main face. The laminate electronic device further comprises a carrier having a first structured metal layer arranged at a first main surface of the carrier. The first structured metal layer is bonded to the electrode pad via a first bond layer of a conductive material, wherein the first bond layer has a thickness of less than 10 ?m. A first insulating layer overlies the first main surface of the carrier and the first semiconductor chip.Type: GrantFiled: January 10, 2012Date of Patent: April 15, 2014Assignee: Infineon Technologies AGInventors: Ewe Henrik, Joachim Mahler, Anton Prueckl, Ivan Nikitin
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Patent number: 8686569Abstract: A die arrangement includes a carrier having a first side and a second side opposite the first side, the carrier including an opening leading from the first side of the carrier to the second side of the carrier; a first die disposed over the first side of the carrier and electrically contacting the carrier; a second die disposed over the second side of the carrier and electrically contacting the carrier; and an electrical contact structure leading through the opening in the carrier and electrically contacting the second die.Type: GrantFiled: December 14, 2010Date of Patent: April 1, 2014Assignee: Infineon Technologies AGInventors: Frank Daeche, Joachim Mahler, Anton Prueckl, Stefan Landau, Josef Hoeglauer
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Patent number: 8664043Abstract: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.Type: GrantFiled: December 1, 2009Date of Patent: March 4, 2014Assignee: Infineon Technologies AGInventors: Henrik Ewe, Joachim Mahler, Anton Prueckl, Stefan Landau
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Patent number: 8648473Abstract: A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side.Type: GrantFiled: March 27, 2012Date of Patent: February 11, 2014Assignee: Infineon Technologies AGInventor: Anton Prueckl
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Publication number: 20130341780Abstract: A chip arrangement is provided. The chip arrangement including: a chip including at least one electrically conductive contact; a passivation material formed over the at least one electrically conductive contact; an encapsulation material formed over the passivation material; one or more holes formed through the encapsulation material and the passivation material, wherein the passivation material at least partially surrounds the one or more holes; and electrically conductive material provided within the one or more holes, wherein the electrically conductive material is electrically connected to the at least one electrically conductive contact.Type: ApplicationFiled: June 20, 2012Publication date: December 26, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Thorsten Scharf, Boris Plikat, Henrik Ewe, Anton Prueckl, Stefan Landau
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Patent number: 8598694Abstract: Various embodiments provide a chip-carrier including, a chip-carrier surface configured to carry a first chip from a first chip bottom side, wherein a first chip top side of the first chip is configured above the chip-carrier surface; and at least one cavity extending into the chip-carrier from the chip-carrier surface; wherein the at least one cavity is configured to carry a second chip from a second chip bottom side, wherein a second chip top side of the second chip is substantially level with the first chip top side. The second chip is electrically insulated from the chip-carrier by an electrical insulation material inside the cavity.Type: GrantFiled: November 22, 2011Date of Patent: December 3, 2013Assignee: Infineon Technologies AGInventors: Khalil Hosseini, Joachim Mahler, Anton Prueckl
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Publication number: 20130256912Abstract: A chip arrangement is provided. The chip arrangement includes: a first chip electrically connected to the first chip carrier top side; a second chip electrically connected to the second chip carrier top side; and electrically insulating material configured to at least partially surround the first chip carrier and the second chip carrier; at least one electrical interconnect configured to electrically contact the first chip to the second chip through the electrically insulating material; one or more first electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier top side and second chip carrier top side, and one or more second electrically conductive portions formed over and electrically contacted to at least one of the first chip carrier bottom side and second chip carrier bottom side.Type: ApplicationFiled: March 27, 2012Publication date: October 3, 2013Applicant: INFINEON TECHNOLOGIES AGInventor: Anton Prueckl
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Publication number: 20130256857Abstract: In one embodiment, a method of forming a semiconductor package comprises providing a first die having contact regions on a top surface but not on an opposite bottom surface. A dielectric liner layer is deposited under the bottom surface of the first die. The first die is attached with the deposited dielectric liner layer to a die paddle of a substrate.Type: ApplicationFiled: March 27, 2012Publication date: October 3, 2013Applicant: Infineon Technologies AGInventors: Hermann Gruber, Joachim Mahler, Uwe Hoeckele, Anton Prueckl, Thomas Fischer, Matthias Schmidt
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Publication number: 20130256856Abstract: An electronic device includes a first chip carrier and a second chip carrier isolated from the first chip carrier. A first power semiconductor chip is mounted on and electrically connected to the first chip carrier. A second power semiconductor chip is mounted on and electrically connected to the second chip carrier. An electrically insulating material is configured to at least partially surround the first power semiconductor chip and the second power semiconductor chip. An electrical interconnect is configured to electrically connect the first power semiconductor chip to the second power semiconductor chip, wherein the electrical interconnect has at least one of a contact clip and a galvanically deposited conductor.Type: ApplicationFiled: March 27, 2012Publication date: October 3, 2013Applicant: Infineon Technologies AGInventors: Joachim Mahler, Thomas Bemmerl, Anton Prueckl
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Publication number: 20130256855Abstract: A chip arrangement is provided, the chip arrangement including: a first chip carrier; a second chip carrier; a first chip electrically connected to the first chip carrier; a second chip disposed over the first chip carrier and electrically insulated from the first chip carrier; and a third chip electrically connected to the second chip carrier; wherein at least one of the first chip and the second chip is electrically connected to the third chip.Type: ApplicationFiled: March 27, 2012Publication date: October 3, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Joachim Mahler, Ralf Wombacher, Anton Prueckl
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Publication number: 20130127031Abstract: Various embodiments provide a chip-carrier including, a chip-carrier surface configured to carry a first chip from a first chip bottom side, wherein a first chip top side of the first chip is configured above the chip-carrier surface; and at least one cavity extending into the chip-carrier from the chip-carrier surface; wherein the at least one cavity is configured to carry a second chip from a second chip bottom side, wherein a second chip top side of the second chip is substantially level with the first chip top side. The second chip is electrically insulated from the chip-carrier by an electrical insulation material inside the cavity.Type: ApplicationFiled: November 22, 2011Publication date: May 23, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Khalil Hosseini, Joachim Mahler, Anton Prueckl
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Publication number: 20130010446Abstract: A laminate electronic device comprises a first semiconductor chip, the first semiconductor chip defining a first main face and a second main face opposite to the first main face, and having at least one electrode pad on the first main face. The laminate electronic device further comprises a carrier having a first structured metal layer arranged at a first main surface of the carrier. The first structured metal layer is bonded to the electrode pad via a first bond layer of a conductive material, wherein the first bond layer has a thickness of less than 10 ?m. A first insulating layer overlies the first main surface of the carrier and the first semiconductor chip.Type: ApplicationFiled: January 10, 2012Publication date: January 10, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Ewe Henrik, Joachim Mahler, Anton Prueckl, Ivan Nikitin
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Publication number: 20120267774Abstract: One aspect is a method of manufacturing a semiconductor device and semiconductor device. One embodiment provides a plurality of modules. Each of the modules includes a carrier and at least one semiconductor chip attached to the carrier. A dielectric layer is applied to the modules to form a workpiece. The dielectric layer is structured to open at least one of the semiconductor chips. The workpiece is singulated to obtain a plurality of devices.Type: ApplicationFiled: June 14, 2012Publication date: October 25, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Henrik Ewe, Joachim Mahler, Anton Prueckl
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Publication number: 20120187565Abstract: A device includes a first semiconductor chip with a first contact pad on a first face and a second semiconductor chip with a first contact pad on a first face. The second semiconductor chip is placed over the first semiconductor chip, wherein the first face of the first semiconductor chip faces the first face of the second semiconductor chip. Exactly one layer of an electrically conductive material is arranged between the first semiconductor chip and the second semiconductor chip. The exactly one layer of an electrically conductive material electrically couples the first contact pad of the first semiconductor chip to the first contact pad of the second semiconductor chip.Type: ApplicationFiled: January 25, 2011Publication date: July 26, 2012Inventors: Henrik Ewe, Joachim Mahler, Anton Prueckl, Stefan Landau
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Patent number: 8201326Abstract: One aspect is a method of manufacturing a semiconductor device and semiconductor device. One embodiment provides a plurality of modules. Each of the modules includes a carrier and at least one semiconductor chip attached to the carrier. A dielectric layer is applied to the modules to form a workpiece. The dielectric layer is structured to open at least one of the semiconductor chips. The workpiece is singulated to obtain a plurality of devices.Type: GrantFiled: December 23, 2008Date of Patent: June 19, 2012Assignee: Infineon Technologies AGInventors: Henrik Ewe, Joachim Mahler, Anton Prueckl
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Publication number: 20120146201Abstract: A die arrangement includes a carrier having a first side and a second side opposite the first side, the carrier including an opening leading from the first side of the carrier to the second side of the carrier; a first die disposed over the first side of the carrier and electrically contacting the carrier; a second die disposed over the second side of the carrier and electrically contacting the carrier; and an electrical contact structure leading through the opening in the carrier and electrically contacting the second die.Type: ApplicationFiled: December 14, 2010Publication date: June 14, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Frank Daeche, Joachim Mahler, Anton Prueckl, Stefan Landau, Josef Hoeglauer
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Patent number: 8120158Abstract: A laminate electronic device comprises a first semiconductor chip, the first semiconductor chip defining a first main face and a second main face opposite to the first main face, and having at least one electrode pad on the first main face. The laminate electronic device further comprises a carrier having a first structured metal layer arranged at a first main surface of the carrier. The first structured metal layer is bonded to the electrode pad via a first bond layer of a conductive material, wherein the first bond layer has a thickness of less than 10 ?m. A first insulating layer overlies the first main surface of the carrier and the first semiconductor chip.Type: GrantFiled: November 10, 2009Date of Patent: February 21, 2012Assignee: Infineon Technologies AGInventors: Henrik Ewe, Joachim Mahler, Anton Prueckl, Ivan Nikitin
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Publication number: 20110127675Abstract: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.Type: ApplicationFiled: December 1, 2009Publication date: June 2, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Henrik Ewe, Joachim Mahler, Anton Prueckl, Stefan Landau
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Publication number: 20110108971Abstract: A laminate electronic device comprises a first semiconductor chip, the first semiconductor chip defining a first main face and a second main face opposite to the first main face, and having at least one electrode pad on the first main face. The laminate electronic device further comprises a carrier having a first structured metal layer arranged at a first main surface of the carrier. The first structured metal layer is bonded to the electrode pad via a first bond layer of a conductive material, wherein the first bond layer has a thickness of less than 10 ?m. A first insulating layer overlies the first main surface of the carrier and the first semiconductor chip.Type: ApplicationFiled: November 10, 2009Publication date: May 12, 2011Applicant: INFINEON TECHNOLOGIES AGInventors: Henrik Ewe, Joachim Mahler, Anton Prueckl, Ivan Nikitin
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Publication number: 20100157568Abstract: One aspect is a method of manufacturing a semiconductor device and semiconductor device. One embodiment provides a plurality of modules. Each of the modules includes a carrier and at least one semiconductor chip attached to the carrier. A dielectric layer is applied to the modules to form a workpiece. The dielectric layer is structured to open at least one of the semiconductor chips. The workpiece is singulated to obtain a plurality of devices.Type: ApplicationFiled: December 23, 2008Publication date: June 24, 2010Applicant: Infineon Technologies AGInventors: Henrik Ewe, Joachim Mahler, Anton Prueckl