Abstract: A system includes a hardware entity that can perform tasks in a secure mode or in an insecure mode. The system's secure resources include a secure memory and a secure logical interface (LIF). The system's insecure resources include an insecure memory and a first insecure LIF. A security mode circuit in the hardware entity can set the hardware entity to secure mode or to insecure mode. Tasks submitted via the secure LIF are performed in secure mode. Tasks submitted via the insecure LIF are performed in insecure mode. The tasks are associated with security mode status indicators that are written to the hardware entities security mode indicator to thereby set the hardware entity into secure mode or insecure mode. The hardware entity cannot access secure resources while in insecure mode.

Abstract: Systems and methods for securely scheduling a remote content capture, and subsequently capturing, securing the captured content and securely transmitting the secured content in an atomic transaction from a second device to a first device. The systems and methods mediate and facilitate contracting for the same. Capture is facilitated without persistence of the captured content on the second device, and the captured content is secured and securely routed to the first device.

Abstract: Systems and methods for securely scheduling a remote content capture, and subsequently capturing, securing the captured content and securely transmitting the secured content in an atomic transaction from a second device to a first device. The systems and methods mediate and facilitate contracting for the same. Capture is facilitated without persistence of the captured content on the second device, and the captured content is secured and securely routed to the first device.

Abstract: Systems and methods for memory replay protection are disclosed. In an example, a system in the form of a device includes a processor, and a replay protection circuit coupled to the processor and including a memory interface circuit, wherein the replay protection circuit is configured to generate a message authentication code (MAC) from at least one block of data and to access the at least one of block of data via the memory interface circuit using ciphertext that is generated by the replay protection circuit in response to a plaintext memory address received from the processor.

Abstract: A system includes a hardware entity that can perform tasks in a secure mode or in an insecure mode. The system's secure resources include a secure memory and a secure logical interface (LIF). The system's insecure resources include an insecure memory and a first insecure LIF. A security mode circuit in the hardware entity can set the hardware entity to secure mode or to insecure mode. Tasks submitted via the secure LIF are performed in secure mode. Tasks submitted via the insecure LIF are performed in insecure mode. The tasks are associated with security mode status indicators that are written to the hardware entities security mode indicator to thereby set the hardware entity into secure mode or insecure mode. The hardware entity cannot access secure resources while in insecure mode.

Abstract: Systems, apparatuses and methods are described for facilitating connection between two or more clients across a network that includes network address translators (NATs). In a particular implementation, the techniques include peer-to-peer (P2P) traffic processing and network address translator (NAT) traversal. Low cost data traffic processing techniques with minimal server intervention are disclosed. The techniques can establish direct connections between clients located in private networks behind NATs. In the case where the clients are each behind a symmetric NAT, the connection can be established indirectly via a non-symmetric NAT (used as a relay) which establishes connection with both symmetric NATs using the disclosed direct connection techniques.