Patents by Inventor Anton Villiers

Anton Villiers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10347742
    Abstract: A method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material. A dummy gate is formed on the replacement gate material over the layered fin structure, wherein the dummy gate having a critical dimension which extends along the length of the layered fin structure. The method further includes forming a gate structure directly under the dummy gate, the gate structure including a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of the dummy gate.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: July 9, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey Smith, Anton Villiers
  • Publication number: 20180138268
    Abstract: A method of fabricating a semiconductor device includes providing a substrate having a layered fin structure thereon. The layered fin structure includes base fin portion, a sacrificial portion provided on the base fin portion and a channel portion provided on the sacrificial portion. A doping source film is provided on the substrate over the layered fin structure, and diffusing doping materials from the doping source film into a portion of the layered fin structure other than the channel portion to form a diffusion doped region in the layered fin structure. An isolation material is provided on the substrate over at least the diffusion doped region of the layered fin structure.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 17, 2018
    Applicant: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton Villiers
  • Publication number: 20180138291
    Abstract: A method of forming a gate-all-around semiconductor device, includes providing a substrate having a layered fin structure thereon. The layered fin structure includes a channel portion and a sacrificial portion each extending along a length of the layered fin structure, wherein the layered fin structure being covered with replacement gate material. A dummy gate is formed on the replacement gate material over the layered fin structure, wherein the dummy gate having a critical dimension which extends along the length of the layered fin structure. The method further includes forming a gate structure directly under the dummy gate, the gate structure including a metal gate region and gate spacers provided on opposing sides of the metal gate region, wherein a total critical dimension of the gate structure is equal to the critical dimension of the dummy gate.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 17, 2018
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Jeffrey Smith, Anton Villiers