Abstract: The present disclosure relates to a ring-oscillator with glitch-free frequency-tuning. The disclosed ring-oscillator at least includes multiple delay stages coupled in series within a ring loop and having a first delay stage, a capacitor bank coupled between an output of the first delay stage and ground, and a timing block configured to receive an output signal of the first delay stage and at least one controlling signal. The at least one controlling signal determines at least one capacitor in the capacitor bank connecting or disconnecting to the ring loop. The timing block is configured to pass or not pass the at least one controlling signal to the capacitor bank based on whether the output signal of the first delay stage meets a certain condition. Therefore, the connection or disconnection of the at least one capacitor does not cause a significant voltage change at the output of the first delay stage.

Abstract: The present disclosure relates to a ring-oscillator with glitch-free frequency-tuning. The disclosed ring-oscillator at least includes multiple delay stages coupled in series within a ring loop and having a first delay stage, a capacitor bank coupled between an output of the first delay stage and ground, and a timing block configured to receive an output signal of the first delay stage and at least one controlling signal. The at least one controlling signal determines at least one capacitor in the capacitor bank connecting or disconnecting to the ring loop. The timing block is configured to pass or not pass the at least one controlling signal to the capacitor bank based on whether the output signal of the first delay stage meets a certain condition. Therefore, the connection or disconnection of the at least one capacitor does not cause a significant voltage change at the output of the first delay stage.

Abstract: The present disclosure relates to a digital subsampling phase-locked-loop (PLL) with a digital-to-time converter (DTC) based successive-approximation-register (SAR) phase estimation. This disclosed PLL utilizes a DTC and a one-bit sampler to generate one phase word by calculating multiple one-bit phase measurements with a SAR algorithm. The one phase word, which indicates the phase estimation of a radio frequency (RF) output signal compared to a reference signal, enables the PLL to lock the RF output signal with the reference signal in a short settling time. In addition, utilizing the one-bit sampler instead of a conventional frequency divider is good for linearity and low power consumption of the PLL without introducing significant noise in the RF output signal.

Abstract: The present disclosure relates to a digital subsampling phase-locked-loop (PLL) with a digital-to-time converter (DTC) based successive-approximation-register (SAR) phase estimation. This disclosed PLL utilizes a DTC and a one-bit sampler to generate one phase word by calculating multiple one-bit phase measurements with a SAR algorithm. The one phase word, which indicates the phase estimation of a radio frequency (RF) output signal compared to a reference signal, enables the PLL to lock the RF output signal with the reference signal in a short settling time. In addition, utilizing the one-bit sampler instead of a conventional frequency divider is good for linearity and low power consumption of the PLL without introducing significant noise in the RF output signal.

Abstract: The present disclosure relates to a frequency locked loop including a frequency detection unit, a local oscillator, and a multi-bit sampler. The frequency detection unit is configured to receive a reference frequency parameter and a sub-sampled frequency parameter, and configured to generate a digital frequency difference, which is a difference indication between the reference frequency parameter and the sub-sampled frequency parameter. The local oscillator is configured to generate an output signal based on the digital frequency difference. The multi-bit sampler is configured to update the sub-sampled frequency parameter by sub-sampling the output signal with N (N>=2) sampling-clocks. The N sampling-clocks have a same sampling frequency and are sequentially offset by an equal time delay between adjacent sampling-clocks. The updated sub-sampled frequency parameter monotonically maps an output frequency of the output signal.

Abstract: Disclosed is a transceiver including a sub-sampling based frequency synthesizer with a sampling frequency fsmp, configured to generate M different output signals 3 for use as a carrier signal for transmission and/or a signal with a channel frequency for reception. M is an integer greater than 4, each output signal has a corresponding predefined frequency. The predefined frequencies are within a frequency band with a predefined bandwidth CFR. CFR is greater than fsmp. The frequency synthesizer includes a frequency shift unit configured for shifting a version of the output signal over a predefined frequency shift fshift to obtain a frequency shifted signal which is supplied to a sampling unit of the sub-sampling based frequency synthesizer, wherein ?fsmp/2?fshift?+fsmp/2. The frequency shift unit is configured to use for the generation of each of the N different output signals a corresponding predefined frequency shift fshift.

Abstract: Disclosed is a transceiver including a sub-sampling based frequency synthesizer with a sampling frequency fsmp, configured to generate M different output signals 3 for use as a carrier signal for transmission and/or a signal with a channel frequency for reception. M is an integer greater than 4, each output signal has a corresponding predefined frequency. The predefined frequencies are within a frequency band with a predefined bandwidth CFR. CFR is greater than fsmp. The frequency synthesizer includes a frequency shift unit configured for shifting a version of the output signal over a predefined frequency shift fshift to obtain a frequency shifted signal which is supplied to a sampling unit of the sub-sampling based frequency synthesizer, wherein ?fsmp/2?fshift?+fsmp/2. The frequency shift unit is configured to use for the generation of each of the N different output signals a corresponding predefined frequency shift fshift.

Abstract: RF power transistor provided with an internal shunt inductor, characterized in that the shunt is produced in two separated, capacitors (Cb, Cp), each internally bonded to the transistor internal active die (AD) through internal leads (Li, Ld1), one of which capacitors (Cp) being connected to the transistor lead (L) by a further bond wire (Ld).

Abstract: RF power transistor provided with an internal shunt inductor, characterized in that the shunt is produced in two separated, capacities (Cb, Cp), each internally bonded to the transistor internal active die (AD) through internal leads (Li, Ld1), one of which capacities (Cp) being connected to the transistor lead (L) by a further bond wire (Ld).