Abstract: A method and semiconductor device for a resonant power converter includes logic circuitry that performs a dedicated startup sequence when power is first provided to the resonant converter. The logic circuitry can discharge the resonant capacitor, then iteratively pulse only an upper switch during a portion of the startup sequence, and measures the dead time between the half bridge signal starting to fall and the next time it finishes rising. If the dead time is greater that a startup exit value, which is based on the most recent upper switch on-time, then the upper switch on-time is incremented and the process is repeated until the dead time is less than the startup exit value, whereupon the startup logic transitions to conventional symmetric switching.

Abstract: A method and semiconductor device for a resonant power converter includes logic circuitry that performs a dedicated startup sequence when power is first provided to the resonant converter. The logic circuitry can discharge the resonant capacitor, then iteratively pulse only an upper switch during a portion of the startup sequence, and measures the dead time between the half bridge signal starting to fall and the next time it finishes rising. If the dead time is greater that a startup exit value, which is based on the most recent upper switch on-time, then the upper switch on-time is incremented and the process is repeated until the dead time is less than the startup exit value, whereupon the startup logic transitions to conventional symmetric switching.

Abstract: In one embodiment, a Schottky diode is formed on a semiconductor substrate with other semiconductor devices and is also formed with a high breakdown voltage and a low forward resistance.

Abstract: In one embodiment, a charge pump circuit is used to keep a boost capacitor of a power supply system charged while the switch transistors are not switching such as when the power supply system is operating in a burst mode of operation.

Abstract: In one embodiment, a power supply controller is configured to switch a power switch of a power supply when a voltage across the switch is at a minimum value.

Abstract: In one embodiment, a Schottky diode is formed on a semiconductor substrate with other semiconductor devices and is also formed with a high breakdown voltage and a low forward resistance.

Abstract: In one embodiment, a Schottky diode structure comprises a Schottky barrier layer in contact with a semiconductor material through a Schottky contact opening. A conductive ring is formed adjacent the Schottky contact opening and is separated from the semiconductor material by a thin insulating layer. Another insulating layer is formed overlying the structure, and a contact opening is formed therein. The contact opening is wider than the Schottky contact opening and exposes portions of the conductive ring. A Schottky barrier metal is formed in contact with the semiconductor material through the Schottky contact opening, and is formed in further+contact with the conductive ring.

Abstract: In one embodiment, a charge pump circuit is used to keep a boost capacitor of a power supply system charged while the switch transistors are not switching such as when the power supply system is operating in a burst mode of operation.

Abstract: In one embodiment, a power supply controller is configured to switch a power switch of a power supply when a voltage across the switch is at a minimum value.

Abstract: In one embodiment, a Schottky diode structure comprises a Schottky barrier layer in contact with a semiconductor material through a Schottky contact opening. A conductive ring is formed adjacent the Schottky contact opening and is separated from the semiconductor material by a thin insulating layer. Another insulating layer is formed overlying the structure, and a contact opening is formed therein. The contact opening is wider than the Schottky contact opening and exposes portions of the conductive ring. A Schottky barrier metal is formed in contact with the semiconductor material through the Schottky contact opening, and is formed in further+contact with the conductive ring.

Abstract: In one embodiment, a voltage translator is configured to sense a change in a value of a supply voltage to the translator and responsively inhibit the translator from changing a state of the output of the translator.

Abstract: In one embodiment, a voltage translator is configured to sense a change in a value of a supply voltage to the translator and responsively inhibit the translator from changing a state of the output of the translator.

Abstract: An integrated detector circuit (20) includes first and second gain stages (GS1, GS2). The first gain stage has an input (82) that monitors a high frequency signal (VRFDET) for routing a first detection current (IS1) to a node (60). The second gain stage includes a first current source (PF1) that supplies a bias current (IMAX1) indicative of a predefined amplitude of the high frequency signal. An input of the second gain stage monitors the high frequency signal to route a portion of the bias current to the node as a second detection current (IS2), which is limited to the bias current when the high frequency signal is greater than the predefined amplitude to compensate for a nonlinearity in a transconductance of the second gain stage.

Abstract: An integrated voltage converter (104) includes a first switch (S1) that turns on with a value of a control signal (UP/DOWN) to generate a coil current (ICOIL) at a node (208) when an output voltage (VOUT) of the voltage converter is greater than a reference voltage (VBATT−&Dgr;V). A second switch (S2) coupled to the node turns on with another value of the control signal to generate the coil current when the output voltage is less than the reference voltage. The coil current discharges through the second switch to an output (202) of the voltage converter to develop the output voltage.

Abstract: An integrated voltage converter (104) includes a first switch (S1) that turns on with a value of a control signal (UP/DOWN) to generate a coil current (ICOIL) at a node (208) when an output voltage (VOUT) of the voltage converter is greater than a reference voltage (VBATT−&Dgr;V). A second switch (S2) coupled to the node turns on with another value of the control signal to generate the coil current when the output voltage is less than the reference voltage. The coil current discharges through the second switch to an output (202) of the voltage converter to develop the output voltage.

Abstract: An integrated detector circuit (20) includes first and second gain stages (GS1, GS2). The first gain stage has an input (82) that monitors a high frequency signal (VRFDET) for routing a first detection current (IS1) to a node (60). The second gain stage includes a first current source (PF1) that supplies a bias current (IMAX1) indicative of a predefined amplitude of the high frequency signal. An input of the second gain stage monitors the high frequency signal to route a portion of the bias current to the node as a second detection current (IS2), which is limited to the bias current when the high frequency signal is greater than the predefined amplitude to compensate for a nonlinearity in a transconductance of the second gain stage.

Abstract: A current sense circuit (14) is provided which receives a signal indicative of output current flow of an up/down DC-DC converter during up-conversion and down-conversion modes. The current sense circuit provides a logic signal (CS) indicative of the rate of change of the current flow for both modes of operation. A comparator (42) receives a selectable voltage reference generated by voltage reference (36,38,50). A first voltage reference is selected during an increasing current flow (CS=logic high) and a second voltage reference is selected during a decreasing current flow (CS=logic low), thereby regulating the output current (IL) to a fixed average value. If the length of time during continuous current flow of converter (10) exceeds a predetermined amount of time, a signal (FAULT) is issued and externally processed, which subsequently disables converter (10) by an external signal (ENABLE).

Abstract: A current sense circuit (14) is provided which receives a signal indicative of output current flow of an up/down DC-DC converter during up-conversion and down-conversion modes. The current sense circuit provides a logic signal (CS) indicative of the rate of change of the current flow for both modes of operation. A comparator (42) receives a selectable voltage reference generated by voltage reference (36,38,50). A first voltage reference is selected during an increasing current flow (CS=logic high) and a second voltage reference is selected during a decreasing current flow (CS=logic low), thereby regulating the output current (IL) to a fixed average value. If the length of time during continuous current flow of converter (10) exceeds a predetermined amount of time, a signal (FAULT) is issued and externally processed, which subsequently disables converter (10) by an external signal (ENABLE).

Abstract: An N-Well bias control circuit (18) is provided which receives a first voltage (VS) and second voltage (VD) of different magnitudes relating to a battery voltage (Vbatt) and an output voltage (Vout) of an up/down DC-DC converter. The bias control circuit provides the voltage of largest magnitude to an output node (VN-Well), which is used to properly bias the N-Well region of a PMOS transistor (26) to minimize the probability of latch up. The N-Well bias control circuit may also be modified to deliver the minimum of two voltages, Vbatt or Vout, to properly bias the P-Well region of an NMOS transistor.

Abstract: A maximum voltage bias control circuit (22) is provided which accepts two supply voltages (Vbatt and Vout) and determines the maximum voltage. The maximum voltage is then applied to terminal (Vmax) with current drivers (46,50) used to provide additional current drive to terminal (Vmax). PMOS transistors (40,42) are used to provide proper N-Well bias control of PMOS transistors (40, 42, 46 and 50).