Abstract: An integrated control circuit for a charge pump includes a first device for regulating the output voltage of the charge pump and a second device for increasing the output voltage from the charge pump with a set ramp. The integrated circuit includes means for activating said first device and providing it with a first value of a supply signal in a first period of time and for activating the second device and providing it with a second value of the supply signal that is greater than the first value in a second period of time after the first in such a way that the output voltage of the charge pump ascends a ramp from a first value to a second value that is greater than the first value, the second value being fixed by reactivation of the first device.

Abstract: A feedback generator of a reference current may include a differential amplifier having a first input for a reference voltage, and a second input for a feedback voltage and generating an output voltage. The feedback generator may also include a first conduction path including a feedback resistor with the feedback voltage applied thereon, and a first transistor controlled by the output voltage and forcing through the feedback resistor the reference current. The feedback generator may also include a second conduction path coupled to the differential amplifier and biasing the differential amplifier based upon the reference current.

Abstract: A memory architecture includes at least one matrix of memory cells of the EEPROM type organized in rows or word lines and columns or bit lines. Each memory cell includes a floating gate cell transistor and a selection transistor and is connected to a source line shared by the matrix. The memory cells are organized in words, all the memory cells belonging to a same word being driven by a byte switch, which is, in turn, connected to at least one control gate line. The memory cells further have accessible substrate terminals connected to a first additional line.

Abstract: A sensing circuit (120) for sensing currents, including: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V?); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and a comparison current generating circuit (N3s, 135; N3s, 135?; N3s, 135?) for generating the comparison current based on a reference current (Ir). The comparison current generating circuit includes at least one voltage generator (135; 135?; 135?). A memory device using the sensing circuit and a method are also provided.

Abstract: A non-volatile memory device is proposed. The memory device includes a plurality of blocks of memory cells, each block having a common biasing node for all the memory cells of the block, biasing means for providing a biasing voltage, and selection means for selectively applying the biasing voltage to the biasing node of a selected block, for each block the selection means including first switching means and second switching means connected in series, the first switching means being connected with the biasing node and the second switching means being connected with the biasing means, wherein the second switching means of all the blocks are connected in parallel, the selection means including means for closing the first switching means of the selected block and the second switching means of all the blocks, and for opening the second switching means of each unselected block.

Abstract: A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a plurality of P-type wells extending in a direction transverse to the rows. A plurality of main bitlines extend along the columns. Each P-type well is associated to a set of local bitlines that extend along the respective P-type well and are coupled to the drain terminals of the cells accommodated in the respective P-type well. Local-bitlines managing circuits are provided for each P-type well and are located between the main bitlines and a respective set of local bitlines for controllably connecting each local bitline to a respective main bitline.

Abstract: A power management unit for a non-volatile memory device is proposed. The power management unit includes means for providing a reference voltage, resistive means for deriving a reference current from the reference voltage, means for generating a plurality of operative voltages from a power supply voltage, and means for regulating the operative voltages; in the power management unit of the invention, for each operative voltage the means for regulating includes means for deriving a scaled reference current from the reference current according to a scaling factor, further resistive means for deriving a rating voltage from the scaled reference current, means for deriving a measuring voltage from the operative voltage and the rating voltage, and means for controlling the operative voltage according to a comparison between the measuring voltage and the reference voltage.

Abstract: An oscillator is provided that includes at least one capacitor, at least one comparator, and at least one device for charging or discharging the at least one capacitor. The capacitor is coupled to the comparator. The comparator compares the voltage on the capacitor with a reference voltage, and activates the device so as to command the charging or the discharging of the capacitor. The oscillator also comprises a circuit for supplying a preset voltage to the comparator when the device commands the charging of the capacitor, so that the comparator compares the reference voltage diminished by the preset voltage with the voltage on the capacitor, or the voltage on the capacitor added to the preset voltage with the reference voltage.

Abstract: A sensing circuit (120) for sensing currents, including: a measure circuit branch (132i), having a measure node for receiving an input current (Ic) to be sensed, for converting the input current into a corresponding input voltage (V?); at least one comparison circuit branch (132o), having a comparison node for receiving a comparison current (Igs), for converting the comparison current into a corresponding comparison voltage (V+); and at least one voltage comparator (140) for comparing the input and comparison voltages, and a comparison current generating circuit (N3s, 135; N3s, 135?; N3s, 135?) for generating the comparison current based on a reference current (Ir). The comparison current generating circuit includes at least one voltage generator (135; 135?; 135?). A memory device using the sensing circuit and a method are also provided.

Abstract: A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a plurality of P-type wells extending in a direction transverse to the rows. A plurality of main bitlines extend along the columns. Each P-type well is associated to a set of local bitlines that extend along the respective P-type well and are coupled to the drain terminals of the cells accommodated in the respective P-type well. Local-bitlines managing circuits are provided for each P-type well and are located between the main bitlines and a respective set of local bitlines for controllably connecting each local bitline to a respective main bitline.

Abstract: A variable charge pump contains several individual simple charge pumps, each with a pumping capacitor and a switching mechanism. Additionally, a switching network is coupled to the individual charge pumps so that the different lines in the charge pump can be connected together in a serial mode or parallel mode (or mixed serial and parallel modes) to match the needs of the output load. The switching network is easily changed to provide the necessary driving capability as the needs of the output load changes.

Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

Abstract: A regulator circuit for a charge pump voltage generator comprises a voltage comparator means for performing a voltage comparison between a charge pump output voltage and a reference voltage, and means responsive to the voltage comparator means for conditioning a charge pump clocking to the result of the voltage comparison. The voltage comparator means includes sampling means for sampling the charge pump output voltage at a sampling rate. Sampling rate control means are provided, responsive to the voltage comparison, for controlling the sampling rate according to the result of the voltage comparison.

Abstract: A circuit for regulating an output voltage of a charge pump includes a regulator connected to an output of the charge pump. The regulator includes a voltage divider for dividing the output voltage. A filter has a first input for receiving the divided output voltage, a second input for receiving a control signal, and an output for providing a filtered divided output voltage. A comparator has a first input for receiving the divided output voltage, a second input for receiving a reference voltage, a third input for receiving the filtered divided output voltage, and an output for providing a digital signal based upon a comparison of the divided output signal, the reference voltage and the filtered divided output voltage. A logic control circuit has a first input for receiving a clock signal, a second input for receiving the digital signal from the comparator, and an output for providing a timing signal.

Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

Abstract: Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells including a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.

Abstract: Bandgap type reference voltage source using an operational transimpedance amplifier. The bandgap stage is formed by a first and a second bandgap branch parallel-connected; the first bandgap branch comprises a first diode and a transistor, series-connected and forming a first output node; the second bandgap branch comprises a second diode and a second transistor series-connected and forming a second output node. The operational amplifier has inputs connected to the output nodes of the bandgap stage. An amplifier current detecting stage is connected to the outputs of the operational amplifier and supplies a current related to the current drawn by the operational amplifier. A diode current detecting stage is connected to the output of the amplifier current detecting stage and to an output of the operational amplifier and supplies a current related to the current flowing in the first diode. An output stage transforms this current into a stabilized voltage.

Abstract: A reading circuit for a memory includes a current detector for each bit line of the memory, a reference voltage generator, and a comparator that compares the reference voltage with the voltage of a reading terminal of the current detector. Each current detector includes a first transistor whose gate is selectively connected to the reading terminal, and whose drain-source path is in series with a respective bit line. An input of a first inverter stage is connected to the source of the first transistor, and an output thereof is connected to the gate of the first transistor. The circuit has a very short reading time based upon each of the current detectors including a first resistor between the source of the first transistor and the bit line, along with second and third transistors having their drain-source paths connected in series with the respective bit line, and along with second and third inverters connected to the respective bit line.

Abstract: A circuit for regulating an output voltage of a charge pump includes a regulator connected to an output of the charge pump. The regulator includes a voltage divider for dividing the output voltage. A filter has a first input for receiving the divided output voltage, a second input for receiving a control signal, and an output for providing a filtered divided output voltage. A comparator has a first input for receiving the divided output voltage, a second input for receiving a reference voltage, a third input for receiving the filtered divided output voltage, and an output for providing a digital signal based upon a comparison of the divided output signal, the reference voltage and the filtered divided output voltage. A logic control circuit has a first input for receiving a clock signal, a second input for receiving the digital signal from the comparator, and an output for providing a timing signal.

Abstract: A sense amplifier for a memory includes a comparator and a bit line polarization circuit. The comparator receives a first signal representative of a current flowing through a memory cell and a second signal representative of a reference current. Additionally, the comparator includes a stage in a common source configuration and an active load for the stage, and the bit line polarization circuit provides a polarization voltage level that is independent of the supply voltage level. In a preferred embodiment, the sense amplifier also includes an output stage that improves switching time at high supply voltages.