Patents by Inventor Antonino Giuseppe LA SPINA

Antonino Giuseppe LA SPINA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory programming techniques
    Patent number: 11061762
    Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Naveen Prabhu Vittal Prabhu, Bharat M. Pathak, Aliasgar S. Madraswala, Yogesh B. Wakchaure, Violante Moschiano, Walter Di Francesco, Michele Incarnati, Antonino Giuseppe La Spina
  • MEMORY PROGRAMMING TECHNIQUES
    Publication number: 20200250028
    Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.
    Type: Application
    Filed: February 4, 2019
    Publication date: August 6, 2020
    Inventors: Naveen Prabhu VITTAL PRABHU, Bharat M. PATHAK, Aliasgar S. MADRASWALA, Yogesh B. WAKCHAURE, Violante MOSCHIANO, Walter DI FRANCESCO, Michele INCARNATI, Antonino Giuseppe LA SPINA