Patents by Inventor Antonino Schillaci
Antonino Schillaci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210273045Abstract: A semiconductor MOS device having an epitaxial layer with a first conductivity type formed by a drain region and by a drift region. The drift region accommodates a plurality of first columns with a second conductivity type and a plurality of second columns with the first conductivity type, the first and second columns alternating with each other and extending on the drain region. Insulated gate regions are each arranged on top of a respective second column; body regions having the second conductivity type extend above and at a distance from a respective first column, thus improving the output capacitance Cds of the device, for use in high efficiency RF applications.Type: ApplicationFiled: May 20, 2021Publication date: September 2, 2021Applicant: STMICROELECTRONICS S.R.L.Inventors: Antonino SCHILLACI, Paola Maria PONZIO, Roberto CAMMARATA
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Patent number: 11024707Abstract: A semiconductor MOS device having an epitaxial layer with a first conductivity type formed by a drain region and by a drift region. The drift region accommodates a plurality of first columns with a second conductivity type and a plurality of second columns with the first conductivity type, the first and second columns alternating with each other and extending on the drain region. Insulated gate regions are each arranged on top of a respective second column; body regions having the second conductivity type extend above and at a distance from a respective first column, thus improving the output capacitance Cds of the device, for use in high efficiency RF applications.Type: GrantFiled: June 11, 2019Date of Patent: June 1, 2021Assignee: STMICROELECTRONICS S.R.L.Inventors: Antonino Schillaci, Paola Maria Ponzio, Roberto Cammarata
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Publication number: 20190386097Abstract: A semiconductor MOS device having an epitaxial layer with a first conductivity type formed by a drain region and by a drift region. The drift region accommodates a plurality of first columns with a second conductivity type and a plurality of second columns with the first conductivity type, the first and second columns alternating with each other and extending on the drain region. Insulated gate regions are each arranged on top of a respective second column; body regions having the second conductivity type extend above and at a distance from a respective first column, thus improving the output capacitance Cds of the device, for use in high efficiency RF applications.Type: ApplicationFiled: June 11, 2019Publication date: December 19, 2019Inventors: Antonino SCHILLACI, Paola Maria PONZIO, Roberto CAMMARATA
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Patent number: 9899508Abstract: Embodiments are directed to super-junction semiconductor devices having an inactive region positioned between active cells. In one embodiment, a semiconductor device is provided that includes a substrate and a drain region on the substrate. The drain region has a first conductivity type. A plurality of first columns is disposed on the drain region, with the first columns having the first conductivity type. A plurality of second columns is disposed on the drain region, with the second columns having a second conductivity type. The first and second columns are alternately arranged such that each of the second columns is positioned between respective first columns. First and second gate structures are included that overlie respective first columns, and a body region is included that has the second conductivity type. The body region abuts at least two second columns and at least one first column positioned between the at least two second columns.Type: GrantFiled: October 10, 2016Date of Patent: February 20, 2018Assignee: STMICROELECTRONICS S.R.L.Inventors: Antonino Schillaci, Paola Maria Ponzio, Alessandro Angelo Alfio Palazzo
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Vertical MOS semiconductor device for high-frequency applications, and related manufacturing process
Patent number: 9508846Abstract: A MOS semiconductor device of a vertical type has: a functional layer, having a first type of conductivity; gate structures, which are formed above the functional layer and have a region of dielectric material and an electrode region; body wells, which have a second type of conductivity, are formed within the functional layer, and are separated by a surface separation region; source regions, which have the first type of conductivity and are formed within the body wells. Each gate structure extends laterally above just one respective body well and does not overlap the surface separation region of the functional layer. The device may further have: at least one shield structure, arranged between adjacent gate structures above the surface separation region; and/or at least one doped control region, having the second type of conductivity, arranged within the surface separation region, which are both set at the source potential.Type: GrantFiled: March 19, 2015Date of Patent: November 29, 2016Assignee: STMicroelectronics S.r.l.Inventors: Antonino Schillaci, Alfonso Patti, Paola Maria Ponzio -
VERTICAL MOS SEMICONDUCTOR DEVICE FOR HIGH-FREQUENCY APPLICATIONS, AND RELATED MANUFACTURING PROCESS
Publication number: 20150303300Abstract: A MOS semiconductor device of a vertical type has: a functional layer, having a first type of conductivity; gate structures, which are formed above the functional layer and have a region of dielectric material and an electrode region; body wells, which have a second type of conductivity, are formed within the functional layer, and are separated by a surface separation region; source regions, which have the first type of conductivity and are formed within the body wells. Each gate structure extends laterally above just one respective body well and does not overlap the surface separation region of the functional layer. The device may further have: at least one shield structure, arranged between adjacent gate structures above the surface separation region; and/or at least one doped control region, having the second type of conductivity, arranged within the surface separation region, which are both set at the source potential.Type: ApplicationFiled: March 19, 2015Publication date: October 22, 2015Inventors: Antonino Schillaci, Alfonso Patti, Paola Maria Ponzio -
Patent number: 8759188Abstract: A method for integrating a bipolar injunction transistor in a semiconductor chip includes the steps of forming an intrinsic base region of a second type of conductivity extending in the collector region from a main surface through an intrinsic base window of the sacrificial insulating layer, forming an emitter region of the first type of conductivity extending in the intrinsic base region from the main surface through an emitter window of the sacrificial insulating layer, removing the sacrificial insulating layer, forming an intermediate insulating layer on the main surface, and forming an extrinsic base region of the second type of conductivity extending in the intrinsic base region from the main surface through an extrinsic base window of the intermediate insulating layer.Type: GrantFiled: December 22, 2011Date of Patent: June 24, 2014Assignees: STMicroelectronics S.r.l., STMicroelectronics Asia Pacific Pte. Ltd.Inventors: Alfonso Patti, Antonino Schillaci, Bartolome Marrone, Gianleonardo Grasso, Rajesh Kumar
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Patent number: 8366941Abstract: A process for exothermic treatment and recovery of masses including: urban solid waste (USW), including differentiated and non-differentiated damp waste and non-differentiated waste of vegetable origin; sludge generated by industrial and non-industrial water treatment; solid, semi-solid, pasty residue and/or sludge residue coming from industrial, agricultural and food-processing operations; soils and inert materials contaminated by organic matrices; solid, semi-solid, pasty residue and/or sludge residue of hydrocarbon compounds, including asphalt and organic-chemical compounds; contaminating animal excrements, such as those of poultry and/or swine. In particular, the process envisages the use of an exothermic reaction produced by mixing the mass to be treated with a mixture of calcium oxides (CaO) and/or calcium hydroxides Ca(OH)2, in the presence of an inert catalyst moistened with water, in the absence of oxygen using the charcoal-pile technique.Type: GrantFiled: March 12, 2008Date of Patent: February 5, 2013Assignee: Antonino SchillaciInventor: Antonino Schillaci
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Publication number: 20120168909Abstract: A method for integrating a bipolar injunction transistor in a semiconductor chip includes the steps of forming an intrinsic base region of a second type of conductivity extending in the collector region from a main surface through an intrinsic base window of the sacrificial insulating layer, forming an emitter region of the first type of conductivity extending in the intrinsic base region from the main surface through an emitter window of the sacrificial insulating layer, removing the sacrificial insulating layer, forming an intermediate insulating layer on the main surface, and forming an extrinsic base region of the second type of conductivity extending in the intrinsic base region from the main surface through an extrinsic base window of the intermediate insulating layerType: ApplicationFiled: December 22, 2011Publication date: July 5, 2012Applicants: STMicroelectronics Asia Pacific Pte. Ltd., STMicroelectronics S.r.l.Inventors: Alfonso Patti, Antonino Schillaci, Bartolome Marrone, Gianleonardo Grasso, Rajesh Kumar
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Publication number: 20100282672Abstract: The present invention refers to a process for exothermal treatment and recovery of masses comprising: urban solid waste (USW—), including differentiated and non-differentiated damp waste and non-differentiated waste of vegetable origin; sludge generated by industrial and non-industrial water treatment; solid, semi-solid, pasty residue and/or sludge residue coming from industrial, agricultural and food-processing operations; soils and inert materials contaminated by organic matrices; solid, semi-solid, pasty residue and/or sludge residue of hydrocarbon compounds, including asphalt and organic-chemical compounds; contaminating animal excrements, such as those of poultry and/or swine. In particular, said process envisages the use of an exothermal reaction produced by mixing the mass to be treated with a mixture of calcium oxides (CaO) and/or calcium hydroxides Ca(OH)2, in the presence of an inert catalyst moistened with water, in the absence of oxygen using the charcoal-pile technique.Type: ApplicationFiled: March 12, 2008Publication date: November 11, 2010Applicant: EB SRL ENVIRONMENTAL BROCKERInventor: Antonino Schillaci
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Patent number: 7186592Abstract: An LDMOS device includes elementary MOS cells. The gate structure of the elementary cell includes a first conductor material finger. The LDMOS device includes first metal stripes for contacting source regions, second metal stripes for contacting drain regions, and third metal stripes placed on inactive zones for contacting a material finger by forming a contact point. The contact point is formed by a first prolongation of the material finger for connecting with one of the third stripes. The third metal stripe includes at least one fourth metal stripe placed on a separation zone. The material finger has a second prolongation and the fourth metal stripe has a first prolongation to form an additional contact point.Type: GrantFiled: April 12, 2005Date of Patent: March 6, 2007Assignee: STMicroelectronics S.r.l.Inventors: Antonino Schillaci, Paola Ponzio
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Publication number: 20050221567Abstract: An LDMOS device includes elementary MOS cells. The gate structure of the elementary cell includes a first conductor material finger. The LDMOS device includes first metal stripes for contacting source regions, second metal stripes for contacting drain regions, and third metal stripes placed on inactive zones for contacting a material finger by forming a contact point. The contact point is formed by a first prolongation of the material finger for connecting with one of the third stripes. The third metal stripe includes at least one fourth metal stripe placed on a separation zone. The material finger has a second prolongation and the fourth metal stripe has a first prolongation to form an additional contact point.Type: ApplicationFiled: April 12, 2005Publication date: October 6, 2005Inventors: Antonino Schillaci, Paola Ponzio
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Patent number: 6933563Abstract: An LDMOS device includes elementary MOS cells. The gate structure of the elementary cell includes a first conductor material finger. The LDMOS device includes first metal stripes for contacting source regions, second metal stripes for contacting drain regions, and third metal stripes placed on inactive zones for contacting a material finger by forming a contact point. The contact point is formed by a first prolongation of the material finger for connecting with one of the third stripes. The third metal stripe includes at least one fourth metal stripe placed on a separation zone. The material finger has a second prolongation and the fourth metal stripe has a first prolongation to form an additional contact point.Type: GrantFiled: September 30, 2003Date of Patent: August 23, 2005Assignee: STMicroelectronics S.R.L.Inventors: Antonino Schillaci, Paola Ponzio
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Patent number: 6919252Abstract: A MOS semiconductor device formed on a substrate of a first conductivity type is provided. The device includes active zones for elementary active elements, and at least one inactive zone suitable for electric signal input or output. The substrate is connected with the drain terminal of the device, and at least one of the elementary active elements includes a body region of a second conductivity type that is connected with the source terminal of the device. The at least one inactive zone includes a semiconductor region of the second conductivity type formed in the substrate and adjacent a surface of the substrate, a conductive layer located over the semiconductor region, and a silicon oxide layer located between the semiconductor region and the conductive layer. The silicon oxide layer has alternating first zones and second zones that are contiguous to each other, with the first zones having a greater thickness than the second zones.Type: GrantFiled: May 21, 2004Date of Patent: July 19, 2005Assignee: STMicroelectronics S.r.l.Inventors: Antonino Schillaci, Paola Maria Ponzio
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Publication number: 20040211984Abstract: A MOS semiconductor device formed on a substrate of a first conductivity type is provided. The device includes active zones for elementary active elements, and at least one inactive zone suitable for electric signal input or output. The substrate is connected with the drain terminal of the device, and at least one of the elementary active elements includes a body region of a second conductivity type that is connected with the source terminal of the device. The at least one inactive zone includes a semiconductor region of the second conductivity type formed in the substrate and adjacent a surface of the substrate, a conductive layer located over the semiconductor region, and a silicon oxide layer located between the semiconductor region and the conductive layer. The silicon oxide layer has alternating first zones and second zones that are contiguous to each other, with the first zones having a greater thickness than the second zones.Type: ApplicationFiled: May 21, 2004Publication date: October 28, 2004Applicant: STMicroelectronics S.r.l.Inventors: Antonino Schillaci, Paola Maria Ponzio
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Patent number: 6750512Abstract: A MOS semiconductor device formed on a substrate of a first conductivity type is provided. The device includes active zones for elementary active elements, and at least one inactive zone suitable for electric signal input or output. The substrate is connected with the drain terminal of the device, and at least one of the elementary active elements includes a body region of a second conductivity type that is connected with the source terminal of the device. The at least one inactive zone includes a semiconductor region of the second conductivity type formed in the substrate and adjacent a surface of the substrate, a conductive layer located over the semiconductor region, and a silicon oxide layer located between the semiconductor region and the conductive layer. The silicon oxide layer has alternating first zones and second zones that are contiguous to each other, with the first zones having a greater thickness than the second zones.Type: GrantFiled: September 20, 2002Date of Patent: June 15, 2004Assignee: STMicroelectronics S.r.l.Inventors: Antonino Schillaci, Paola Maria Ponzio
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Publication number: 20040094806Abstract: An LDMOS device includes elementary MOS cells. The gate structure of the elementary cell includes a first conductor material finger. The LDMOS device includes first metal stripes for contacting source regions, second metal stripes for contacting drain regions, and third metal stripes placed on inactive zones for contacting a material finger by forming a contact point. The contact point is formed by a first prolongation of the material finger for connecting with one of the third stripes. The third metal stripe includes at least one fourth metal stripe placed on a separation zone. The material finger has a second prolongation and the fourth metal stripe has a first prolongation to form an additional contact point.Type: ApplicationFiled: September 30, 2003Publication date: May 20, 2004Inventors: Antonino Schillaci, Paola Ponzio
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Publication number: 20030075739Abstract: A MOS semiconductor device formed on a substrate of a first conductivity type is provided. The device includes active zones for elementary active elements, and at least one inactive zone suitable for electric signal input or output. The substrate is connected with the drain terminal of the device, and at least one of the elementary active elements includes a body region of a second conductivity type that is connected with the source terminal of the device. The at least one inactive zone includes a semiconductor region of the second conductivity type formed in the substrate and adjacent a surface of the substrate, a conductive layer located over the semiconductor region, and a silicon oxide layer located between the semiconductor region and the conductive layer. The silicon oxide layer has alternating first zones and second zones that are contiguous to each other, with the first zones having a greater thickness than the second zones.Type: ApplicationFiled: September 20, 2002Publication date: April 24, 2003Applicant: STMICROELECTRONICS S.r.I.Inventors: Antonino Schillaci, Paola Maria Ponzio
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Patent number: 6365930Abstract: Semiconductor device for high voltages including at least one power component and at least one edge termination. The edge termination includes a voltage divider including a plurality of MOS transistors in series, and the edge termination is connected between non-driveble terminals of said power component.Type: GrantFiled: June 1, 2000Date of Patent: April 2, 2002Assignee: STMicroelectronics S.r.l.Inventors: Antonino Schillaci, Antonio Grimaldi, Giuseppe Ferla
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Patent number: 6111297Abstract: A MOS-technology power device integrated structure includes a first plurality of elongated doped semiconductor stripes of a first conductivity type formed in a semiconductor layer of a second conductivity type, each including an elongated source region of the first conductivity type, an annular doped semiconductor region of the first conductivity type formed in the semiconductor layer and surrounding and merged with the elongated stripes, insulated gate stripes extending over the semiconductor layer between adjacent elongated stripes, a plurality of conductive gate fingers extending over and electrically connected to the insulated gate stripes, and a plurality of source metal fingers, each one extending over a respective elongated stripe and contacting the elongated stripe and the respective elongated source region, so that the source metal fingers and the conductive gate fingers are interdigitated.Type: GrantFiled: May 28, 1998Date of Patent: August 29, 2000Assignee: Consorzio per la Ricerca sulla Microelettronica nel MezzogiornoInventors: Antonio Grimaldi, Antonino Schillaci