Patents by Inventor Antonio B. Dimaano Jr.

Antonio B. Dimaano Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7830020
    Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: November 9, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Frederick Rodriguez Dahilig, Sheila Marie L. Alvarez, Antonio B. Dimaano, Jr., Dioscoro A. Merilo
  • Publication number: 20100264528
    Abstract: A method for manufacturing an integrated circuit package system includes: providing a base package having a first integrated circuit with an inner lead on a periphery thereof and connected thereto with interconnects, and the inner lead partially encapsulated by an inner encapsulation; mounting an outer lead on the periphery of the base package; mounting a second integrated circuit above the base package and connected to the outer lead with the interconnects; and partially encapsulating, the base package and the outer leads with an outer encapsulation leaving a bottom surface of the inner lead and a bottom surface of the outer lead exposed.
    Type: Application
    Filed: June 30, 2010
    Publication date: October 21, 2010
    Inventors: Dioscoro A. Merilo, Antonio B. Dimaano, JR.
  • Publication number: 20100219523
    Abstract: A stackable integrated circuit package system includes: a substrate having a first side and a second side opposite the first side, the substrate having a cavity provided therein; a first integrated circuit die in the cavity with a first interconnect extending out from the cavity without connection and a second interconnect connected to the first side; a first mold compound to cover the first integrated circuit die, the second interconnect, and a portion of the first interconnect; a second integrated circuit die mounted to the first integrated circuit die with a third interconnect connected to the second side; a second mold compound to cover the second integrated circuit die and the third interconnect; and external interconnects, not encapsulated by the second encapsulant, mounted on the second side.
    Type: Application
    Filed: May 10, 2010
    Publication date: September 2, 2010
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Dioscoro A. Merilo, Antonio B. Dimaano, JR.
  • Patent number: 7777320
    Abstract: An integrated circuit package system includes: providing a base package having a first integrated circuit with an inner lead on a periphery thereof and connected thereto with interconnects, and the inner lead partially encapsulated by an inner encapsulation; mounting an outer lead on the periphery of the base package; mounting a second integrated circuit above the base package and connected to the outer lead with the interconnects; and partially encapsulating, the base package and the outer leads with an outer encapsulation leaving a bottom surface of the inner lead and a bottom surface of the outer lead exposed.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: August 17, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Dioscoro A. Merilo, Antonio B. Dimaano, Jr.
  • Patent number: 7741707
    Abstract: A stackable integrated circuit package system is provided placing a first integrated circuit die having an interconnect provided thereon in a substrate having a cavity, encapsulating the first integrated circuit die, having the interconnect exposed, in the cavity and along a first side of the substrate, mounting a second integrated circuit die to the first integrated circuit die, and encapsulating the second integrated circuit die along a second side of the substrate.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: June 22, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Dioscoro A. Merilo, Antonio B. Dimaano, Jr.
  • Publication number: 20100072586
    Abstract: An integrated circuit package system includes: providing a base package having a first integrated circuit with an inner lead on a periphery thereof and connected thereto with interconnects, and the inner lead partially encapsulated by an inner encapsulation; mounting an outer lead on the periphery of the base package; mounting a second integrated circuit above the base package and connected to the outer lead with the interconnects; and partially encapsulating, the base package and the outer leads with an outer encapsulation leaving a bottom surface of the inner lead and a bottom surface of the outer lead exposed.
    Type: Application
    Filed: September 23, 2008
    Publication date: March 25, 2010
    Inventors: Dioscoro A. Merilo, Antonio B. Dimaano, JR.
  • Publication number: 20090230529
    Abstract: A method of manufacture of an integrated circuit packaging system is provided including: forming a D-ring includes half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring.
    Type: Application
    Filed: May 27, 2009
    Publication date: September 17, 2009
    Inventors: Antonio B. Dimaano, JR., Il Kwon Shim, Sheila Rima C. Magno
  • Patent number: 7556987
    Abstract: An integrated circuit package system is provided including forming a D-ring comprising half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: July 7, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Antonio B. Dimaano, Jr., Il Kwon Shim, Sheila Rima C. Magno
  • Patent number: 7545032
    Abstract: An integrated circuit package system is provided including forming a mounting structure having an external interconnect, a paddle, and a tie bar; mounting an integrated circuit die on the paddle; soldering a stiffener structure; having an opening; on the mounting structure; connecting the stiffener structure to a ground; and molding the integrated circuit die and partially the stiffener structure through the opening.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: June 9, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Henry D. Bathan, Antonio B. Dimaano, Jr., Jeffrey D. Punzalan, Zigmund Ramirez Camacho
  • Patent number: 7541222
    Abstract: A method for manufacturing a wire sweep resistant semiconductor package provides a die attached to an interposer. The die is electrically connected to the interposer with conductive wires. A sealant is applied on the die at the conductive wires for preventing wire sweep and the sealant is free of contact with the interposer. The die, the interposer, the conductive wires, and the sealant are encapsulated in an encapsulant.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: June 2, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Sheila Rima C. Magno, Byung Tai Do, Dennis Guillermo, Antonio B. Dimaano, Jr.
  • Publication number: 20090079049
    Abstract: An integrated circuit package system includes: providing an integrated circuit wafer having an active side and a backside; forming a stress-relieving layer on the backside; forming an adhesion layer on the stress-relieving layer; dicing the integrated circuit wafer into a semiconductor chip with the stress-relieving layer and the adhesion layer on the backside of the semiconductor chip; and mounting the semiconductor chip over electrical interconnects.
    Type: Application
    Filed: September 20, 2007
    Publication date: March 26, 2009
    Inventors: Byung Tai Do, Il Kwon Shim, Antonio B. Dimaano, JR., Heap Hoe Kuan
  • Patent number: 7482683
    Abstract: An integrated circuit encapsulation system with vent is provided including providing a sheet material, forming a leadframe array on the sheet material, forming a leadframe air vent on the leadframe array, attaching an integrated circuit to the leadframe array, mounting the leadframe array in a mold and encapsulating the integrated circuit and the leadframe array.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: January 27, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Antonio B. Dimaano, Jr., Erick Dahilig, Sheila Marie L. Alvarez, Robinson Quiazon, Jose Alvin Caparas
  • Patent number: 7479692
    Abstract: An integrated circuit package system is provided including forming a paddle, forming a ring with a recess in the paddle, mounting a device in the recess, forming a slot in the ring, and mounting a heat sink in the slot over the device.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: January 20, 2009
    Assignee: Stats Chippac Ltd.
    Inventors: Antonio B. Dimaano, Jr., Il Kwon Shim, Henry D. Bathan, Jeffrey D. Punzalan
  • Publication number: 20090008768
    Abstract: A semiconductor package system including: providing a substrate having a thermal relief thereon; depositing a mask on the substrate and the thermal relief, the mask deposited on the thermal relief and having a regular pattern to partially cover the thermal relief; and die attaching a semiconductor die over the thermal relief.
    Type: Application
    Filed: July 5, 2007
    Publication date: January 8, 2009
    Inventors: Leocadio M. Alabin, Librado Gatbonton, Chiu Hsieh Ong, Beng Yee Teh, Antonio B. Dimaano, JR.
  • Publication number: 20080315411
    Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including an inner lead-finger system and an outer lead-finger system; stacking a first device, a second device, and a third device between and over the electrical interconnect system; connecting the first device and the second device to the inner lead-finger system; and connecting the third device to the outer lead-finger system.
    Type: Application
    Filed: June 21, 2007
    Publication date: December 25, 2008
    Inventors: Frederick Rodriguez Dahilig, Sheila Marie L. Alvarez, Antonio B. Dimaano, JR., Dioscoro A. Merilo
  • Publication number: 20080284038
    Abstract: An integrated circuit package system is provided including forming a perimeter paddle having a first external interconnect extending therefrom, mounting an integrated circuit die over the perimeter paddle, connecting a second external interconnect and the integrated circuit die, and encapsulating the integrated circuit die and the perimeter paddle with the first external interconnect exposed.
    Type: Application
    Filed: May 16, 2007
    Publication date: November 20, 2008
    Inventors: Antonio B. Dimaano, JR., Sheila Marie L. Alvarez
  • Patent number: 7385299
    Abstract: A stackable integrated circuit package system is provided forming a first integrated circuit die having an interconnect provided thereon, forming an external interconnect, having an upper tip and a lower tip, from a lead frame, mounting the first integrated circuit die on the external interconnect with the interconnect on the lower tip and below the upper tip, and encapsulating around the interconnect with an exposed surface.
    Type: Grant
    Filed: February 25, 2006
    Date of Patent: June 10, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Dioscoro A. Merilo, Antonio B. Dimaano, Jr.
  • Patent number: 7141886
    Abstract: A die is attached to a substrate and is enclosed in a heat spreader, the heat spreader having a first encapsulant guide and a heat spreader air vent in the heat spreader extending therethrough. An encapsulant encapsulates the die, the substrate, at least a portion of the heat spreader, the first encapsulant guide, and the heat spreader air vent such that the encapsulant enters the heat spreader through the first encapsulant guide and air exits the heat spreader through the heat spreader air vent, thus preventing the formation of air pockets under the heat spreader.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: November 28, 2006
    Assignee: Stats Chippac Ltd.
    Inventors: Antonio B. Dimaano, Jr., Byung Tai Do, Dennis Guillermo, Sheila Rima C. Magno
  • Patent number: 6969640
    Abstract: A die is attached to a substrate and is enclosed in a heat spreader, the heat spreader having a first encapsulant guide and a heat spreader air vent in the heat spreader extending therethrough. An encapsulant encapsulates the die, the substrate, at least a portion of the heat spreader, the first encapsulant guide, and the heat spreader air vent such that the encapsulant enters the heat spreader through the first encapsulant guide and air exits the heat spreader through the heat spreader air vent, thus preventing the formation of air pockets under the heat spreader.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: November 29, 2005
    Assignee: Stats Chippac Ltd.
    Inventors: Antonio B. Dimaano Jr., Byung Tai Do, Dennis Guillermo, Sheila Rima C. Magno
  • Patent number: 6543127
    Abstract: In accordance with the objectives of the invention a new method and apparatus is provide for assuring contact balls coplanarity. The process and apparatus for coplanarity inspection is integrated with the current processing step of BGA device singulation and pick-and-place, thereby eliminating the need for a separate processing step that is typically required for the coplanarity inspection.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: April 8, 2003
    Assignee: St Assembly Test Service Ltd.
    Inventors: Antonio B. Dimaano, Jr., Weddie Pacio Aquien, John Briar