Abstract: A method and circuit for in-service testing of the winding of electromagnetic actuators and the like having a known effective response time and being connected between an energy supply and actuating circuit means, including driving the input of the actuating circuit means with a test signal similar to the effective actuating signal and limited to a duration shorter than the effective response time of the actuator; and activating return circuit means between the winding and the output of the actuating circuit means, by the winding current flow upon termination of the test signal whereby the flow of component self-induction current through the return circuit means furnishes a pulse signal output for checking the efficiency and integrity of the actuating circuit means, the electromagnetic actuator, and the electrical circuit connections therebetween without producing an erroneous intervention. An effective intervention may be produced by overriding the test signal with a control intervention signal.

Abstract: A circuit for the in-service testing of a logic timer generating an internally-preset time-delayed output logic state in response to a timer control input logic state, including a first logic operator having an output equal to the logic product of the negation of the timer control logic input and an enable signal derived from the negation of the timer logic output; a second logic operator having an output which is the timer control logic input and is equal to the logic sum of a master input logic signal plus the output of the first logic operator; and a delay generator having an input which is the timer output logic signal and having an output which delays the return transition of the first logic operator output for a fixed duration of time less than the effective time required for actuation of the timer output load, whereby a master input logic state of duration greater than the time internal delay period produces a timer output logic state which begins at the end of the internal time-delay period and which

Abstract: A bistable logic circuit generating a stable, preferred output logic state for activating a circuit load having a known response time and capable of being tested while installed and in service without activating the output load includes preferential output state logic memory means, asymmetric delay means and first logic means to generate an output which is the logic product of the memory output and the negation of the circuit Reset input. Second logic means generates the memory means control signal as the logic sum of the circuit Set input and the circuit output asymmetrically delayed by a time period less than the load response time. A test pulse output having a time duration less than the load response time is generated for a set input having a time duration less than one internally determined time period whereby the circuit load is not activated.