Patents by Inventor Antonio Castro

Antonio Castro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180253676
    Abstract: A device may receive multiple data elements related to a technical capability of resources of an organization. The technical capability may be associated with gathering, storing, processing, or providing data. The multiple data elements may be received from a hardware resource of the organization. The device may store the multiple data elements in a storage device associated with a cloud computing environment. The storage device may store multiple other data elements associated with another organization. The device may perform an analysis of the multiple data elements to identify a deficiency related to the technical capability of resources of the organization. The device may generate multiple action items to perform based on identifying the deficiency, where the multiple action items are to reduce the deficiency. The device may perform an action associated with the multiple action items to positively impact the deficiency.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 6, 2018
    Inventors: Mallory SHETH, Elliot Brook, Robert E. Berkey, Scott Alister, Chad Vaske, Powell Jones, Antonio Castro
  • Patent number: 9229720
    Abstract: A high volume manufacturing (HVM) and circuit marginality validation (CMV) test for an integrated circuit (IC) is disclosed. The IC comprises a port binding and bubble logic in the front end to provide flexibility in binding a port to the uop and to create empty spaces (bubbles) in the uop flow. The out-of-order (OOO) cluster of the IC comprises reservation disable logic to control the flow sequence of the uops and stop schedule logic to temporarily stop dispatching the uops from the OOO cluster to the execution (EXE) cluster. The EXE cluster of the IC comprises signal event uops to generate fault information and fused uJump uops to specify combination of branch prediction, direction, and resolution in any portion of the test. Such features provide a tester the flexibility to perform HVM and CMV testing of the OOO and EXE clusters of the IC.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: January 5, 2016
    Assignee: Intel Corporation
    Inventors: Antonio Castro, Mohammad Al-Aqrabawi, Brad A. Kelly, Rehan Sheikh
  • Publication number: 20080244235
    Abstract: A high volume manufacturing (HVM) and circuit marginality validation (CMV) test for an integrated circuit (IC) is disclosed. The IC comprises a port binding and bubble logic in the front end to provide flexibility in binding a port to the uop and to create empty spaces (bubbles) in the uop flow. The out-of-order (OOO) cluster of the IC comprises reservation disable logic to control the flow sequence of the uops and stop schedule logic to temporarily stop dispatching the uops from the OOO cluster to the execution (EXE) cluster. The EXE cluster of the IC comprises signal event uops to generate fault information and fused uJump uops to specify combination of branch prediction, direction, and resolution in any portion of the test. Such features provide a tester the flexibility to perform HVM and CMV testing of the OOO and EXE clusters of the IC.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Inventors: Antonio Castro, Mohammad Al-Aqrabawi, Brad A. Kelly, Rehan Sheikh