Patents by Inventor Antonio Dimaano

Antonio Dimaano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090236726
    Abstract: A semiconductor package that includes a substrate having first and second major surfaces is presented. The package includes a plurality of landing pads and a semiconductor die disposed on the first major surface. A molded cap is disposed on the first surface to encapsulate the die and substrate. The landing pads are covered when the cap is molded. Package interconnects are coupled to the landing pads. The package interconnects are exposed by the cap to facilitate package stacking.
    Type: Application
    Filed: December 12, 2008
    Publication date: September 24, 2009
    Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.
    Inventors: Danny RETUTA, Hien Boon TAN, Yi Sheng Anthony SUN, Librado Amurao GATBONTON, Antonio DIMAANO, JR.
  • Patent number: 7456496
    Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: November 25, 2008
    Assignee: Advanpack Solutions Pte Ltd
    Inventors: Tan Kim Hwee, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano
  • Publication number: 20070262423
    Abstract: An integrated circuit encapsulation system with vent is provided including providing a sheet material, forming a leadframe array on the sheet material, forming a leadframe air vent on the leadframe array, attaching an integrated circuit to the leadframe array, mounting the leadframe array in a mold and encapsulating the integrated circuit and the leadframe array.
    Type: Application
    Filed: May 12, 2006
    Publication date: November 15, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Antonio Dimaano, Erick Dahilig, Sheila Marie Alvarez, Robinson Quiazon, Jose Caparas
  • Publication number: 20070210443
    Abstract: An integrated circuit package on package system including forming an interconnect integrated circuit package and attaching an extended-lead integrated circuit package on the interconnect integrated circuit package wherein a mold cap of the extended-lead integrated circuit package faces a mold cap of the interconnect integrated circuit package.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 13, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Dioscoro Merilo, Seng Guan Chow, Antonio Dimaano, Heap Hoe Kuan, Tsz Yin Ho
  • Publication number: 20070210424
    Abstract: An integrated circuit package in package system including forming a base integrated circuit package with a base lead having a portion with a substantially planar base surface, forming an extended-lead integrated circuit package with an extended lead having a portion with a substantially planar lead-end surface, and stacking the extended-lead integrated circuit package over the base integrated circuit package with the substantially planar lead-end surface coplanar with the substantially planar base surface.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 13, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Tsz Yin Ho, Dioscoro Merilo, Seng Guan Chow, Antonio Dimaano, Heap Hoe Kuan
  • Publication number: 20070209834
    Abstract: An integrated circuit leaded stacked package system including forming an no-lead integrated circuit package having a mold cap, and attaching a mold cap of an extended-lead integrated circuit package facing the mold cap of the no-lead integrated circuit package.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 13, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Heap Hoe Kuan, Tsz Yin Ho, Dioscoro Merilo, Seng Guan Chow, Antonio Dimaano
  • Publication number: 20070200230
    Abstract: A stackable integrated circuit package system is provided placing a first integrated circuit die having an interconnect provided thereon in a substrate having a cavity, encapsulating the first integrated circuit die, having the interconnect exposed, in the cavity and along a first side of the substrate, mounting a second integrated circuit die to the first integrated circuit die, and encapsulating the second integrated circuit die along a second side of the substrate.
    Type: Application
    Filed: February 27, 2006
    Publication date: August 30, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Dioscoro Merilo, Antonio Dimaano
  • Publication number: 20070200257
    Abstract: A stackable integrated circuit package system is provided forming a first integrated circuit die having an interconnect provided thereon, forming an external interconnect, having an upper tip and a lower tip, from a lead frame, mounting the first integrated circuit die on the external interconnect with the interconnect on the lower tip and below the upper tip, and encapsulating around the interconnect with an exposed surface.
    Type: Application
    Filed: February 25, 2006
    Publication date: August 30, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Dioscoro Merilo, Antonio Dimaano
  • Publication number: 20070075404
    Abstract: An integrated circuit package system is provided including an integrated circuit package system including an integrated circuit and a lead frame. The lead frame has a multi-surface die attach pad and the integrated circuit is mounted to the multi-surface die attach pad.
    Type: Application
    Filed: October 3, 2005
    Publication date: April 5, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Antonio Dimaano, Il Kwon Shim, Sheila Rima Magno, Dennis Guillermo
  • Publication number: 20070063354
    Abstract: A method for manufacturing a wire sweep resistant semiconductor package provides a die attached to an interposer. The die is electrically connected to the interposer with conductive wires. A sealant is applied on the die at the conductive wires for preventing wire sweep and the sealant is free of contact with the interposer. The die, the interposer, the conductive wires, and the sealant are encapsulated in an encapsulant.
    Type: Application
    Filed: September 11, 2006
    Publication date: March 22, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Sheila Rima Magno, Byung Tai Do, Dennis Guillermo, Antonio Dimaano
  • Publication number: 20060043612
    Abstract: A method for manufacturing a wire sweep resistant semiconductor package provides a die attached to an interposer. The die is electrically connected to the interposer with conductive wires. A sealant is applied to the conductive wires and optionally the die to prevent wire sweep, the sealant being applied free of contact with the interposer. The die, the interposer, the conductive wires, and the sealant are enclosed in an encapsulant.
    Type: Application
    Filed: September 2, 2004
    Publication date: March 2, 2006
    Applicant: STATS ChipPAC Ltd.
    Inventors: Sheila Magno, Byung Tai Do, Dennis Guillermo, Antonio Dimaano
  • Publication number: 20060043564
    Abstract: A die is attached to a substrate and is enclosed in a heat spreader, the heat spreader having a first encapsulant guide and a heat spreader air vent in the heat spreader extending therethrough. An encapsulant encapsulates the die, the substrate, at least a portion of the heat spreader, the first encapsulant guide, and the heat spreader air vent such that the encapsulant enters the heat spreader through the first encapsulant guide and air exits the heat spreader through the heat spreader air vent, thus preventing the formation of air pockets under the heat spreader.
    Type: Application
    Filed: August 29, 2005
    Publication date: March 2, 2006
    Applicant: STATS ChipPAC Ltd.
    Inventors: Antonio Dimaano, Byung Do, Dennis Guillermo, Sheila Rima Magno
  • Publication number: 20050205987
    Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
    Type: Application
    Filed: May 12, 2005
    Publication date: September 22, 2005
    Inventors: Tan Hwee, Roman Perez, Kee Lau, Alex Chew, Antonio Dimaano
  • Patent number: 6929981
    Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: August 16, 2005
    Assignee: Advanpack Solutions PTE, Ltd.
    Inventors: Tan Kim Hwee, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano
  • Publication number: 20050087883
    Abstract: A design and method of fabrication for a semiconductor package is described. A solder bumped semiconductor chip is assembled to a metallized package substrate utilizing the solder bumps. The interconnecting solder bumps are properly constrained at assembly by the introduction of a no-flow underfill between the chip and the substrate. The no-flow underfill constrains the solder of the solder bumps so as to maintain the desired size and shape.
    Type: Application
    Filed: October 22, 2003
    Publication date: April 28, 2005
    Inventors: Tan Hwee, Roman Perez, Antonio Dimaano, Lau Kwang, Alex Chew
  • Publication number: 20040108580
    Abstract: A semiconductor chip packaging structure is described. The structure comprising of a semiconductor chip interconnected to a recessed lead frame and the resultant assembly encapsulated in a molding compound. The final product is a reverse mounted semiconductor chip in a leadless quad flat pack configuration. A second embodiment allows for the semiconductor chip backside to be exposed for thermal enhancements. Manufacturing methods are also described for the two embodiments disclosed.
    Type: Application
    Filed: December 9, 2002
    Publication date: June 10, 2004
    Applicant: Advanpack Solutions Pte. Ltd.
    Inventors: Kim Hwee Tan, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano
  • Patent number: 6734039
    Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: May 11, 2004
    Assignee: Advanpack Solutions Pte Ltd.
    Inventors: Tan Kim Hwee, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano
  • Publication number: 20040046238
    Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 11, 2004
    Applicant: Advanpack Solutions Pte Ltd.
    Inventors: Tan Kim Hwee, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano
  • Publication number: 20040046257
    Abstract: A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 11, 2004
    Applicant: Advanpack Solutions Pte.Ltd.
    Inventors: Tan Kim Hwee, Roman Perez, Kee Kwang Lau, Alex Chew, Antonio Dimaano