Patents by Inventor Antonio Fischetti

Antonio Fischetti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11343187
    Abstract: There is disclosed an example of a host computing apparatus, including: an exact match cache (EMC) to perform exact matching according to an exact match tuple; a datapath classifier (DPCLS) to provide wildcard searching in a tuple search space (TSS) including a plurality of subtables, the subtables having one or more rule masks; a controller to receive a first packet having a first property matching a first rule of the classifier table, and forward header data of the packet to a partial rule module (PRM); and the PRM to compute a quantitative distance between the first rule and the exact match tuple of the EMC, and to execute a flow action for the first packet according to the quantitative distance.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventor: Antonio Fischetti
  • Patent number: 11201940
    Abstract: Technologies for flow rule aware exact match cache compression include multiple computing devices in communication over a network. A computing device reads a network packet from a network port and extracts one or more key fields from the packet to generate a lookup key. The key fields are identified by a key field specification of an exact match flow cache. The computing device may dynamically configure the key field specification based on an active flow rule set. The computing device may compress the key field specification to match a union of non-wildcard fields of the active flow rule set. The computing device may expand the key field specification in response to insertion of a new flow rule. The computing device looks up the lookup key in the exact match flow cache and, if a match is found, applies the corresponding action. Other embodiments are described and claimed.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventors: Yipeng Wang, Ren Wang, Antonio Fischetti, Sameh Gobriel, Tsung-Yuan C. Tai
  • Publication number: 20190095442
    Abstract: Various embodiments are generally directed to techniques to determine a profile of locations of misses among a plurality of iterative locations for a plurality of search keys, the plurality of locations corresponding with sub-keys within the search keys, the profile of location of misses based on comparisons of sub-key hash values with element hash values indicating sub-key hash values and corresponding element hash values do not match, wherein the sub-key hash values are based on sub-keys of the plurality of search keys, and the element hash values are based on elements of entries of a table, utilize the profile of locations of misses to identify a location to perform a direct match operation, and perform the direct match operation at the location, the direct match operation to determine at the location whether a sub-key of a search key matches an element of one or more entries in the table.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 28, 2019
    Applicant: INTEL CORPORATION
    Inventor: ANTONIO FISCHETTI
  • Publication number: 20190052719
    Abstract: Technologies for flow rule aware exact match cache compression include multiple computing devices in communication over a network. A computing device reads a network packet from a network port and extracts one or more key fields from the packet to generate a lookup key. The key fields are identified by a key field specification of an exact match flow cache. The computing device may dynamically configure the key field specification based on an active flow rule set. The computing device may compress the key field specification to match a union of non-wildcard fields of the active flow rule set. The computing device may expand the key field specification in response to insertion of a new flow rule. The computing device looks up the lookup key in the exact match flow cache and, if a match is found, applies the corresponding action. Other embodiments are described and claimed.
    Type: Application
    Filed: January 4, 2018
    Publication date: February 14, 2019
    Inventors: Yipeng Wang, Ren Wang, Antonio Fischetti, Sameh Gobriel, Tsung-Yuan C. Tai
  • Publication number: 20190044856
    Abstract: There is disclosed an example of a host computing apparatus, including: an exact match cache (EMC) to perform exact matching according to an exact match tuple; a datapath classifier (DPCLS) to provide wildcard searching in a tuple search space (TSS) including a plurality of subtables, the subtables having one or more rule masks; a controller to receive a first packet having a first property matching a first rule of the classifier table, and forward header data of the packet to a partial rule module (PRM); and the PRM to compute a quantitative distance between the first rule and the exact match tuple of the EMC, and to execute a flow action for the first packet according to the quantitative distance.
    Type: Application
    Filed: December 5, 2017
    Publication date: February 7, 2019
    Inventor: Antonio Fischetti
  • Patent number: 10187308
    Abstract: A virtual switch configured to switch packets between virtual switch ports based on classifier sub-tables. The virtual switch reserves blocks of last level cache for classifier sub-table storage. The virtual switch also maintains a global sub-table priority map for the classifier sub-tables. The global sub-table priority map indicates usage frequency of each classifier sub-table when switching the packets between the ports. A sub-set of the classifier sub-tables with a highest usage frequency, according to the global sub-table priority map, are pre-fetched to the reserved blocks of the last level cache. By pre-fetching the most used classifier sub-tables, memory related bottlenecks are reduced when searching through classifier sub-tables. This mechanism increases processing speed when matching packets/flows to classifier sub-tables, resulting in faster packet switching by the virtual switch.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: January 22, 2019
    Assignee: Intel Corporation
    Inventors: Bhanu Prakash Bodi Reddy, Jasvinder Singh, Antonio Fischetti
  • Publication number: 20180097728
    Abstract: A virtual switch configured to switch packets between virtual switch ports based on classifier sub-tables. The virtual switch reserves blocks of last level cache for classifier sub-table storage. The virtual switch also maintains a global sub-table priority map for the classifier sub-tables. The global sub-table priority map indicates usage frequency of each classifier sub-table when switching the packets between the ports. A sub-set of the classifier sub-tables with a highest usage frequency, according to the global sub-table priority map, are pre-fetched to the reserved blocks of the last level cache. By pre-fetching the most used classifier sub-tables, memory related bottlenecks are reduced when searching through classifier sub-tables. This mechanism increases processing speed when matching packets/flows to classifier sub-tables, resulting in faster packet switching by the virtual switch.
    Type: Application
    Filed: November 16, 2016
    Publication date: April 5, 2018
    Applicant: Intel Corporation
    Inventors: Bhanu Prakash Bodi Reddy, Jasvinder Singh, Antonio Fischetti