Abstract: To perform a lookup for a group of plural portions of data in a cache together, a first part of an identifier for a first one of the portions of data in the group is compared with corresponding first parts of the identifiers for cache lines in the cache, the first part of the identifier for the first one of the portions of data in the group is compared with the corresponding first parts of the identifiers for the remaining portions of data in the group of plural portions of data, and a remaining part of the identifier for each portion of data is compared with the corresponding remaining parts of identifiers for cache lines in the cache. It is then determined whether a cache line for any of the portions of data in the group is present in the cache, based on the results of the comparisons.

Abstract: To perform a lookup for a group of plural portions of data in a cache together, a first part of an identifier for a first one of the portions of data in the group is compared with corresponding first parts of the identifiers for cache lines in the cache, the first part of the identifier for the first one of the portions of data in the group is compared with the corresponding first parts of the identifiers for the remaining portions of data in the group of plural portions of data, and a remaining part of the identifier for each portion of data is compared with the corresponding remaining parts of identifiers for cache lines in the cache. It is then determined whether a cache line for any of the portions of data in the group is present in the cache, based on the results of the comparisons.

Abstract: In a data processor comprising a processing pass circuit and a cache, a record of processing passes to be performed by the processing pass circuit is stored, including storing, for each processing pass recorded in the buffer: information indicative of any data that is required for performing the processing pass that is not yet stored in the cache, including an identifier for any data that is required for performing the processing pass that is not yet stored in the cache. When new data to perform a processing pass is loaded into the cache, an identifier for that new data is compared to any identifiers for data that processing passes in the processing pass record are waiting for, and the information indicative of any data that is required for performing processing passes that is not yet stored in the cache stored in the processing pass record is updated.

Abstract: Cache storage comprising cache lines, each configured to store respective data entries. The cache storage is configured to store a tag in the form of: an individual tag portion which is individual to a cache line; a shareable tag portion which is shareable between cache lines; and pointer data which associates an individual tag portion with a shareable tag portion.

Abstract: In a data processing system, mapping circuitry is provided to map one of J first identifiers received from an upstream component to one of K second identifiers to be provided to a downstream component (K<J). K mapping entries are each associated with a respective second identifier and each store mapping information for identifying which first identifier is mapped to the associated second identifier. For a first subset of mapping entries, allocation circuitry prevents allocation of a given first identifier to a mapping entry of the first subset other than a selected group of one or more mapping entries of the first subset selected based on the given first identifier. For a second subset of mapping entries associated with a second subset of the K second identifiers, the allocation circuitry permits the given first identifier to be allocated to any mapping entry in the second subset.

Abstract: A method can include allowing re-use of a selected shareable tag storage location and thus updating a first shareable tag portion comprised therein to a second shareable tag portion; identifying one or more cache lines associated with individual tag portions comprising a pointer to the selected shareable tag storage location; and setting a given cache line status for each of the identified cache lines, wherein the given cache line status: a) allows a cache line to continue to be used in relation to a storage access instruction received before said given cache line status was set; and b) inhibits the cache line from being used in relation to a storage access instruction received after the given cache line status is set.

Abstract: A cache is disclosed in which a dedicated cache portion comprising one or more extra lines dedicated for data of a particular data type is provided alongside a shared cache portion. So long as there is a cache line available in the shared cache portion, data can be written into the shared cache portion. However, when the shared cache portion is fully locked such that no new data can be written into the shared cache portion, data can instead be written to its respective dedicated cache portion, effectively bypassing the fully locked shared cache portion.

Abstract: To determine whether a first n-bit binary data value and a second n-bit binary data value in a data processing system, such as texel position coordinates in a graphics processing system, are the same or differ from each other by exactly one, it is determined whether the first and second data values excluding the least significant bits of the data values are the same as each other, and the least significant bits of the data values are compared. A mask value that is generated for each data value using an XOR operation and a thermometer scanning operation is used to generate an output value for the two data values, based on whether the mask values for a bit position for the first and second data values are both set or not, and a comparison of the bit values of the first and second data values for that bit position.

Abstract: A cache is disclosed in which a dedicated cache portion comprising one or more extra lines dedicated for data of a particular data type is provided alongside a shared cache portion. So long as there is a cache line available in the shared cache portion, data can be written into the shared cache portion. However, when the shared cache portion is fully locked such that no new data can be written into the shared cache portion, data can instead be written to its respective dedicated cache portion, effectively bypassing the fully locked shared cache portion.

Abstract: In a data processing system, mapping circuitry is provided to map one of J first identifiers received from an upstream component to one of K second identifiers to be provided to a downstream component (K<J). K mapping entries are each associated with a respective second identifier and each store mapping information for identifying which first identifier is mapped to the associated second identifier. For a first subset of mapping entries, allocation circuitry prevents allocation of a given first identifier to a mapping entry of the first subset other than a selected group of one or more mapping entries of the first subset selected based on the given first identifier. For a second subset of mapping entries associated with a second subset of the K second identifiers, the allocation circuitry permits the given first identifier to be allocated to any mapping entry in the second subset.

Abstract: Cache storage comprising cache lines, each configured to store respective data entries. The cache storage is configured to store a tag in the form of: an individual tag portion which is individual to a cache line; a shareable tag portion which is shareable between cache lines; and pointer data which associates an individual tag portion with a shareable tag portion.

Abstract: A method can include allowing re-use of a selected shareable tag storage location and thus updating a first shareable tag portion comprised therein to a second shareable tag portion; identifying one or more cache lines associated with individual tag portions comprising a pointer to the selected shareable tag storage location; and setting a given cache line status for each of the identified cache lines, wherein the given cache line status: a) allows a cache line to continue to be used in relation to a storage access instruction received before said given cache line status was set; and b) inhibits the cache line from being used in relation to a storage access instruction received after the given cache line status is set.

Abstract: A method of operating a data processing system comprises maintaining record of a set of processing passes to be performed by processing pass circuitry of the data processing system. The method comprises performing cycles of operation in which it is considered whether or not the data required for a subset of processing passes is stored in a local cache. The subset of processing passes that is considered in a subsequent scan of the record comprises at least one processing pass that was not considered in the previous scan of the record, regardless of whether or not the data considered in the previous scan is determined as being stored in the cache. The method provides an efficient way to identify processing passes that are ready to be performed.