Abstract: The circuit distributes a test signal applied to a pad of an electronic device that is enabled during test phases of the device and disabled during normal functioning. The circuit includes a “master” buffer, one or more “slave” buffers, one for each replicated pad, and an interconnection bus of the “master” and “slave” buffers. During a test phase, the “master” buffer replicates on the interconnection bus the test signal fed to a pad of the device, while the “slave” buffers convey to the various replica pads of the feed pad the signal present on the interconnection bus. During the normal operation of the device, the circuit remains disabled.

Abstract: A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels.

Abstract: The circuit distributes a test signal applied to a pad of an electronic device that is enabled during test phases of the device and disabled during normal functioning. The circuit includes a “master” buffer, one or more “slave” buffers, one for each replicated pad, and an interconnection bus of the “master” and “slave” buffers. During a test phase, the “master” buffer replicates on the interconnection bus the test signal fed to a pad of the device, while the “slave” buffers convey to the various replica pads of the feed pad the signal present on the interconnection bus. During the normal operation of the device, the circuit remains disabled.

Abstract: A non-volatile memory device suitable to be programmed in a sequential mode. The device includes a plurality of blocks of memory cells each one for storing a word, each block being identified by an address. An input circuit for loading an input address at the beginning of a programming procedure and an internal circuit for setting an internal address to the input address. The device further includes a data input circuit for loading a predetermined number of input words in succession, and a latch circuit for latching a page consisting of the predetermined number of input words. The memory then executes a programming operation including writing the page in the blocks identified by consecutive addresses starting from the internal address, and increments the internal address of the predetermined number in response to the completion of the programming operation.

Abstract: A method for management of the programming controls in a multilevel device is provided. During the control step cells are not controlled all together but they are conveniently selected in order to reduce the source resistance and consumption effect, but without penalizing change times.

Abstract: A method for management of the programming controls in a multilevel device is provided. During the control step cells are not controlled all together but they are conveniently selected in order to reduce the source resistance and consumption effect, but without penalizing change times.

Abstract: A non-volatile memory device suitable to be programmed in a sequential mode. The device includes a plurality of blocks of memory cells each one for storing a word, each block being identified by an address. An input circuit for loading an input address at the beginning of a programming procedure and an internal circuit for setting an internal address to the input address. The device further includes a data input circuit for loading a predetermined number of input words in succession, and a latch circuit for latching a page consisting of the predetermined number of input words. The memory then executes a programming operation including writing the page in the blocks identified by consecutive addresses starting from the internal address, and increments the internal address of the predetermined number in response to the completion of the programming operation.

Abstract: A method for reading data from an integrated electronic memory device including a non-volatile memory matrix includes supplying the memory with an address of a memory location where a reading is to be effected, accessing the memory matrix in a random read mode, supplying the memory with a clock signal and an address acknowledge signal (LAN), detecting a request for burst read mode access, and starting the burst reading as the clock signal shows a rising edge. A related circuit is also provided.