Patents by Inventor Antonio Geremia
Antonio Geremia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11809141Abstract: A time-to-digital converter (TDC) uses voltage as a representation of time offset. A voltage change is induced over a time period from a start signal to a stop signal. The final voltage is then measured, and the voltage measurement is mapped to a time value representing the time between the start signal and the stop signal. The voltage change can be increasing or decreasing, e.g., by charging or discharging a capacitive circuit between the start signal and the stop signal. The voltage can be measured using an analog-to-digital converter (ADC) or other voltage measurement circuit. The voltage measurement can be mapped to the time value in any manner, such as, for example, using a transfer function or using a mapping table that provides a time value for each possible voltage measurement value.Type: GrantFiled: March 1, 2022Date of Patent: November 7, 2023Assignee: Anokiwave, Inc.Inventors: Kartik Sridharan, Jun Li, Eythan Familier, Gaurav Menon, Shamsun Nahar, Akhil Garlapati, Scott Humphreys, Antonio Geremia
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Patent number: 11743026Abstract: Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.Type: GrantFiled: February 28, 2022Date of Patent: August 29, 2023Assignee: Anokiwave, Inc.Inventors: Kartik Sridharan, Jun Li, Gaurav Menon, Shamsun Nahar, Akhil Garlapati, Scott Humphreys, Antonio Geremia
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Publication number: 20220303112Abstract: Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.Type: ApplicationFiled: February 28, 2022Publication date: September 22, 2022Applicant: Anokiwave, Inc.Inventors: Kartik Sridharan, Jun Li, Gaurav Menon, Shamsun Nahar, Akhil Garlapati, Scott Humphreys, Antonio Geremia
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Publication number: 20220283550Abstract: A time-to-digital converter (TDC) uses voltage as a representation of time offset. A voltage change is induced over a time period from a start signal to a stop signal. The final voltage is then measured, and the voltage measurement is mapped to a time value representing the time between the start signal and the stop signal. The voltage change can be increasing or decreasing, e.g., by charging or discharging a capacitive circuit between the start signal and the stop signal. The voltage can be measured using an analog-to-digital converter (ADC) or other voltage measurement circuit. The voltage measurement can be mapped to the time value in any manner, such as, for example, using to a transfer function or using a mapping table that provides a time value for each possible voltage measurement value.Type: ApplicationFiled: March 1, 2022Publication date: September 8, 2022Inventors: Kartik Sridharan, Jun Li, Eythan Familier, Gaurav Menon, Shamsun Nahar, Akhil Garlapati, Scott Humphreys, Antonio Geremia
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Publication number: 20220286140Abstract: Digital post-processing of time-to-digital converter (TDC) output data can be used to map each TDC code to the ideal one, but this requires knowing the TDC input-output mapping. Therefore, a calibration system and method are provided for characterizing operation of a TDC to compensate for non-idealities. Input signals having a known time difference are provided to the TDC, and a mapping between the TDC output and the known time difference is stored in a mapping table. With the described method, it is possible to input an input ramp of very low slope to construct this mapping to a desired resolution during a background calibration procedure. This characterizing and mapping can be performed across a range of input signals having different known time differences. After calibration, a mapping table can be used by a mapping circuit of the TDC or by a digital post-processing function to provide a compensated TDC output.Type: ApplicationFiled: March 1, 2022Publication date: September 8, 2022Inventors: Eythan Familier, Kartik Sridharan, Jun Li, Gaurav Menon, Shamsun Nahar, Akhil Garlapati, Scott Humphreys, Antonio Geremia
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Patent number: 11296860Abstract: Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.Type: GrantFiled: July 17, 2020Date of Patent: April 5, 2022Assignee: Anokiwave, Inc.Inventors: Kartik Sridharan, Jun Li, Gaurav Menon, Shamsun Nahar, Akhil Garlapati, Scott Humphreys, Antonio Geremia
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Publication number: 20210021402Abstract: Embodiments of the present invention synchronize multiple synthesizers, such as phase-locked loops (PLLs), in a manner that does not require communication or coordination between the synthesizers. Specifically, each synthesizer is part of a synthesizer circuit that includes a synthesizer (e.g., a PLL), a phase measurement circuit, and a synchronization circuit. A common reference signal (e.g., an alternating clock signal) is provided to the synthesizer circuits. In one exemplary embodiment, in each synthesizer circuit, the phase measurement circuit measures a phase difference between the reference signal and a corresponding output of the synthesizer, and the synchronization circuit adjusts the synthesizer operation based on the measured phase difference in such a way that all of the synthesizers operate in-phase with one another relative to the common reference signal, without having any communication or coordination between the two synthesizer circuits other than provision of the common reference signal.Type: ApplicationFiled: July 17, 2020Publication date: January 21, 2021Inventors: Kartik Sridharan, Jun Li, Gaurav Menon, Shamsun Nahar, Akhil Garlapati, Scott Humphreys, Antonio Geremia
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Patent number: 9133702Abstract: An alternative piston pump employed in mechanical pumping systems for oil extraction. The alternative piston pump includes a case part having at least one cavity disposed along its inner surface. Thus, during the pumping cycle, a gas transfer from a bottom chamber to the case part above a piston and an oil transfer from the case part above the piston to the bottom chamber is established.Type: GrantFiled: September 8, 2011Date of Patent: September 15, 2015Assignee: Rijeza Industria Metalurgica LTDAInventor: Ivo Antonio Geremia
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Publication number: 20130160642Abstract: The actual patent refers to an invention for alternative piston pump (40) improvement, and particularly to an alternative piston pump (40) improvement employed in mechanical pumping systems for oil extraction, aiming to solve the shutdown on gas in fluid elevation draining problem. The proposed improvement is characterized by the alternative piston pump (40) case (41) to be provided with at least one cavity (46) disposed along its inner surface (411). Thus, during the pumping cycle, a gas transfer from bottom chamber (45) to the case part (41) above piston (42) and an oil transfer from the case part (41) above the piston (42) to the bottom chamber (45) is established. Therefore solving the shutdown on gas in fluid elevation draining problem, for oil extraction mechanical pumping systems.Type: ApplicationFiled: September 8, 2011Publication date: June 27, 2013Applicant: RIJEZA INDUSTRIA METALURGICA LTDAInventor: Ivo Antonio Geremia