Abstract: A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.

Abstract: The present invention generally relates to compositions and methods for determining kinase activity. In some cases, the compositions comprise a triazole heterocycle. In some embodiments, the compositions comprise a quinoline moiety. In one aspect, the present invention is directed to compositions that undergo chelation-enhanced fluorescence (CHEF). In some cases, the compositions may have fluorescence emission spectra with peak maxima greater than 490 nm. The compositions of the present invention can be used, in certain embodiments, to detect phosphorylated substrates and biological processes such as phosphorylation events.

Abstract: Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.

Abstract: The present invention relates to a bituminous composition comprising at least one bitumen and at least one polycondensate capable of forming a supramolecular assembly comprising one or more associative group(s). The present invention also relates to the use of such bituminous composition for the preparation of asphalt mixtures useful for the coating of rolling surfaces, for the preparation of water-proofing coatings, and the for the preparation of adhesive formulations.

Abstract: This invention relates to the modification of bitumen by polymeric materials used particularly for the preparation of asphalt mixtures with enhanced mechanical properties, wherein the polymeric materials are selected from additives capable of forming a supramolecular assembly. The modified bitumen may be used for the fabrication of asphalts mixtures with mineral aggregates used in construction or maintenance of sidewalks, roads, highways, parking lots or airport runaways and service roads and any other rolling surfaces.

Abstract: The present invention relates to bitumen additive mixtures, their use and application for the fabrication of asphalt mixtures used in pavement and waterproofing, and more specifically for construction, repair and maintenance of sidewalks, roads, highways, parking lots or airport runaways and service roads and any other rolling surfaces.

Abstract: Embodiments of systems and methods presently disclosed generally relate to categorizing penalty costs associated with calls. More specifically, embodiments relate to identifying penalty costs generated in response to setting up calls in a network and determining one or more reasons for the penalty costs. Further still, embodiments relate to generating one or more reports of penalty costs. Further yet, embodiments relate to notifying specified personnel of the penalty cost report(s).

Abstract: The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.

Abstract: Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.

Abstract: Methods and apparatus are disclosed for using a register checkpointing mechanism to resolve multithreading mis-speculations. Valid architectural state is recovered and execution is rolled back. Some embodiments include memory to store checkpoint data. Multiple thread units concurrently execute threads. They execute a checkpoint mask instruction to initialize memory to store active checkpoint data including register contents and a checkpoint mask indicating the validity of stored register contents. As register contents change, threads execute checkpoint write instructions to store register contents and update the checkpoint mask. Threads also execute a recovery function instruction to store a pointer to a checkpoint recovery function, and in response to mis-speculation among the threads, branch to the checkpoint recovery function.

Abstract: The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.

Abstract: Methods and apparatus to provide leakage power estimation are described. In one embodiment, one or more sensed temperature values (108) and one or more voltage values (110) are utilized to determine the leakage power of an integrated circuit (IC) component. Other embodiments are also described.

Abstract: Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.

Abstract: Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.

Abstract: In one embodiment, the present invention includes a method for determining if data of a memory request by a first agent is in a memory region represented by a region indicator of a region table of the first agent, and transmitting a compressed address for the memory request to other agents of a system if the memory region is represented by the region indicator, otherwise transmitting a full address. Other embodiments are described and claimed.

Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.

Abstract: In one embodiment, the present invention includes a method for protecting a value to be stored in a register of a register file with a first level of protection if the value is predicted to be used for a first time period, and protecting the value with a second level of protection if the value is predicted to be used for a second time period. Other embodiments are described and claimed.

Abstract: A sensor assembly includes a lead frame holding a Hall sensor. The lead frame is sandwiched between top and bottom unitarily molded plastic holder halves to protect the lead frame during subsequent overmolding.

Abstract: An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.

Abstract: In some embodiments, an apparatus for an energy efficient clustered micro-architecture are disclosed. In one embodiment, the micro-architecture computes an energy delay2 product for each active instruction scheduler and one or more associated function blocks of a current architecture configuration over a predetermined period. Once the energy delay2 product is computed, the computed product is compared against an energy delay2 product calculated for a prior architecture configuration to determine an effectiveness (energy efficiency) of the current architecture configuration. Based on the effectiveness of the current architecture configuration, a number of active instruction schedulers and one or more associated functional blocks within the current architecture configuration is adjusted. In one embodiment, the number of active instruction schedulers and one or more associated functional blocks may be increased or decreased to improve power efficiency of the cluster micro-architecture.