Patents by Inventor Antonio Gonzalez

Antonio Gonzalez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110053180
    Abstract: The present invention generally relates to compositions and methods for determining kinase activity. In some cases, the compositions comprise a triazole heterocycle. In some embodiments, the compositions comprise a quinoline moiety. In one aspect, the present invention is directed to compositions that undergo chelation-enhanced fluorescence (CHEF). In some cases, the compositions may have fluorescence emission spectra with peak maxima greater than 490 nm. The compositions of the present invention can be used, in certain embodiments, to detect phosphorylated substrates and biological processes such as phosphorylation events.
    Type: Application
    Filed: August 31, 2010
    Publication date: March 3, 2011
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: BARBARA IMPERIALI, ELVEDIN LUKOVIC, JUAN ANTONIO GONZALEZ-VERA
  • Patent number: 7895415
    Abstract: Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: February 22, 2011
    Assignee: Intel Corporation
    Inventors: Antonio Gonzalez, Josep M. Codina, Pedro Lopez, Fernando Latorre, Jose-Alejandro Pineiro, Enric Gibert, Jaume Abella, Jaideep Moses, Donald Newell, Ravishankar Iyer, Ramesh G. Illikkal, Srihari Makineni
  • Publication number: 20110034593
    Abstract: The present invention relates to a bituminous composition comprising at least one bitumen and at least one polycondensate capable of forming a supramolecular assembly comprising one or more associative group(s). The present invention also relates to the use of such bituminous composition for the preparation of asphalt mixtures useful for the coating of rolling surfaces, for the preparation of water-proofing coatings, and the for the preparation of adhesive formulations.
    Type: Application
    Filed: August 3, 2010
    Publication date: February 10, 2011
    Applicant: CECA S.A.
    Inventors: Juan Antonio Gonzalez Leon, Jean-Philippe Gillet, Gilles Barreto, Manuel Hidalgo, Vincent Luca
  • Publication number: 20110009533
    Abstract: This invention relates to the modification of bitumen by polymeric materials used particularly for the preparation of asphalt mixtures with enhanced mechanical properties, wherein the polymeric materials are selected from additives capable of forming a supramolecular assembly. The modified bitumen may be used for the fabrication of asphalts mixtures with mineral aggregates used in construction or maintenance of sidewalks, roads, highways, parking lots or airport runaways and service roads and any other rolling surfaces.
    Type: Application
    Filed: February 20, 2009
    Publication date: January 13, 2011
    Inventors: Juan Antonio Gonzalez Leon, Gilles Barreto, Lionel Grampre
  • Publication number: 20110005429
    Abstract: The present invention relates to bitumen additive mixtures, their use and application for the fabrication of asphalt mixtures used in pavement and waterproofing, and more specifically for construction, repair and maintenance of sidewalks, roads, highways, parking lots or airport runaways and service roads and any other rolling surfaces.
    Type: Application
    Filed: July 6, 2010
    Publication date: January 13, 2011
    Applicant: CECA S.A.
    Inventors: Juan Antonio Gonzalez Leon, Gilles Barreto, Vincent Luca, Eric Jorda
  • Publication number: 20110007880
    Abstract: Embodiments of systems and methods presently disclosed generally relate to categorizing penalty costs associated with calls. More specifically, embodiments relate to identifying penalty costs generated in response to setting up calls in a network and determining one or more reasons for the penalty costs. Further still, embodiments relate to generating one or more reports of penalty costs. Further yet, embodiments relate to notifying specified personnel of the penalty cost report(s).
    Type: Application
    Filed: July 9, 2009
    Publication date: January 13, 2011
    Applicant: LEVEL 3 COMMUNICATIONS, LLC
    Inventors: Michelle Gore, Jose Antonio Gonzalez
  • Publication number: 20100332811
    Abstract: The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.
    Type: Application
    Filed: September 10, 2010
    Publication date: December 30, 2010
    Inventors: Hong Wang, Tor M. Aamodt, Pedro Marcuello, Jared W. Stark, IV, John P. Shen, Antonio Gonzalez, Per Hammarlund, Gerolf F. Hoflehner, Perry H. Wang, Steve Shih-wei Liao
  • Publication number: 20100269102
    Abstract: Systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads are described. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads. A merging level cache (MLC) merges data from the lines of the DCUs. An inter-core memory coherency module (ICMC) globally retire instructions of the speculatively executed threads in the MLC.
    Type: Application
    Filed: November 24, 2009
    Publication date: October 21, 2010
    Inventors: Fernando Latorre, Josep M. Codina, Enric Gibert Codina, Pedro Lopez, Carlos Madriles, Alejandro Martinez Vincente, Raul Martinez, Antonio Gonzalez
  • Publication number: 20100262812
    Abstract: Methods and apparatus are disclosed for using a register checkpointing mechanism to resolve multithreading mis-speculations. Valid architectural state is recovered and execution is rolled back. Some embodiments include memory to store checkpoint data. Multiple thread units concurrently execute threads. They execute a checkpoint mask instruction to initialize memory to store active checkpoint data including register contents and a checkpoint mask indicating the validity of stored register contents. As register contents change, threads execute checkpoint write instructions to store register contents and update the checkpoint mask. Threads also execute a recovery function instruction to store a pointer to a checkpoint recovery function, and in response to mis-speculation among the threads, branch to the checkpoint recovery function.
    Type: Application
    Filed: April 8, 2009
    Publication date: October 14, 2010
    Inventors: Pedro Lopez, Carlos Madriles, Alejandro Martinez, Raul Martinez, Josep M. Codina, Enric Gibert Codina, Fernando Latorre, Antonio Gonzalez
  • Patent number: 7814469
    Abstract: The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: October 12, 2010
    Assignee: Intel Corporation
    Inventors: Hong Wang, Tor M. Aamodt, Pedro Marcuello, Jared W. Stark, IV, John P. Shen, Antonio González, Per Hammarlund, Gerolf F. Hoflehner, Perry H. Wang, Steve Shih-wei Liao
  • Patent number: 7814339
    Abstract: Methods and apparatus to provide leakage power estimation are described. In one embodiment, one or more sensed temperature values (108) and one or more voltage values (110) are utilized to determine the leakage power of an integrated circuit (IC) component. Other embodiments are also described.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: October 12, 2010
    Assignee: Intel Corporation
    Inventors: Pedro Chaparro Monferrer, Grigorios Magklis, Jose Gonzalez, Antonio Gonzalez
  • Publication number: 20100115247
    Abstract: Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.
    Type: Application
    Filed: October 31, 2008
    Publication date: May 6, 2010
    Inventors: Pedro Lopez, F. Jesus Sanchez, Josep M. Codina, Enric Gibert, Fernando Latorre, Grigorios Magklis, Pedro Marcuello, Antonio Gonzalez
  • Publication number: 20100115224
    Abstract: Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.
    Type: Application
    Filed: October 30, 2008
    Publication date: May 6, 2010
    Inventors: Jaume Abella, Xavier Vera, Javier Carretero Casado, Pedro Chaparro Monferrer, Antonio Gonzalez
  • Patent number: 7698512
    Abstract: In one embodiment, the present invention includes a method for determining if data of a memory request by a first agent is in a memory region represented by a region indicator of a region table of the first agent, and transmitting a compressed address for the memory request to other agents of a system if the memory region is represented by the region indicator, otherwise transmitting a full address. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Grigorios Magklis, Jose Gonzalez, Pedro Chaparro, Qiong Cai, Antonio Gonzalez
  • Publication number: 20100082905
    Abstract: Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
    Type: Application
    Filed: September 30, 2008
    Publication date: April 1, 2010
    Inventors: Christopher Wilkerson, Muhammad M. Khellah, Vivek De, Ming Zhang, Jaume Abella, Javier Carretero Casado, Pedro Chaparro Monferrer, Xavier Vera, Antonio Gonzalez
  • Patent number: 7689804
    Abstract: In one embodiment, the present invention includes a method for protecting a value to be stored in a register of a register file with a first level of protection if the value is predicted to be used for a first time period, and protecting the value with a second level of protection if the value is predicted to be used for a second time period. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: March 30, 2010
    Assignee: Intel Corporation
    Inventors: Xavier Vera, Jaume Abella, Jose-Alejandro Pineiro, Antonio Gonzalez, Ronny Ronen
  • Publication number: 20100059654
    Abstract: A sensor assembly includes a lead frame holding a Hall sensor. The lead frame is sandwiched between top and bottom unitarily molded plastic holder halves to protect the lead frame during subsequent overmolding.
    Type: Application
    Filed: September 5, 2008
    Publication date: March 11, 2010
    Inventors: Antonio Gonzalez, Tania C. Vazquez, Salvador Sandoval, Cruz Gerardo Gonzalez, Oscar Gonzalez
  • Patent number: 7665000
    Abstract: An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: February 16, 2010
    Assignee: Intel Corporation
    Inventors: Antonio Gonzalez, Qiong Cai, Jose Gonzalez, Pedro Chaparro, Grigorios Magklis, Ryan Rakvic
  • Patent number: 7657766
    Abstract: In some embodiments, an apparatus for an energy efficient clustered micro-architecture are disclosed. In one embodiment, the micro-architecture computes an energy delay2 product for each active instruction scheduler and one or more associated function blocks of a current architecture configuration over a predetermined period. Once the energy delay2 product is computed, the computed product is compared against an energy delay2 product calculated for a prior architecture configuration to determine an effectiveness (energy efficiency) of the current architecture configuration. Based on the effectiveness of the current architecture configuration, a number of active instruction schedulers and one or more associated functional blocks within the current architecture configuration is adjusted. In one embodiment, the number of active instruction schedulers and one or more associated functional blocks may be increased or decreased to improve power efficiency of the cluster micro-architecture.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: February 2, 2010
    Assignee: Intel Corporation
    Inventors: Jose Gonzalez, Antonio Gonzalez
  • Publication number: 20100005277
    Abstract: In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed.
    Type: Application
    Filed: October 27, 2006
    Publication date: January 7, 2010
    Inventors: Enric Gibert, Josep M. Codina, Fernando Latorre, José Alejandro Pineiro, Pedro López, Antonio González