Patents by Inventor Antonio Griseta

Antonio Griseta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ECC for single 4-bits symbol correction of 32 symbols words with 21 maximum row weight matrix
    Patent number: 7996745
    Abstract: An error correction device is provided. Such error correction device may make use of an error correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 21.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: August 9, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonio Griseta, Antonio Lonigro, Angelo Mazzone
  • ECC for single 4-bits symbol correction of 32 symbols words with 22 maximum row weight matrix
    Patent number: 7996748
    Abstract: An error correction device is provided. Such error correction device may make use of an error-correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 22.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: August 9, 2011
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Antonio Griseta, Angelo Mazzone
  • Built-in self test circuit for integrated circuits
    Patent number: 7213185
    Abstract: A built-in self-test circuit adapted to be embedded in an integrated circuit for testing the integrated circuit, including in particular a collection of addressable elements, for example a semiconductor memory. The BIST circuit comprises a general-purpose data processor programmable for executing a test program for testing the integrated circuit. The BIST circuit comprises an accelerator circuit cooperating with the general-purpose data processor for autonomously conducting operations on the integrated circuit according to the test program. The accelerator circuit comprises configuration means adapted to be loaded with configuration parameters for adapting the accelerator circuit to the specific type of integrated circuit and the specific type of test program.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: May 1, 2007
    Assignee: STMicroelectronics S.r.l
    Inventors: Massimiliano Barone, Antonio Griseta
  • ECC for single 4-bits symbol correction of 32 symbols words with 21 maximum row weight matrix
    Publication number: 20070016843
    Abstract: An error correction device is provided. Such error correction device may make use of an error correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 21.
    Type: Application
    Filed: May 19, 2006
    Publication date: January 18, 2007
    Inventors: Antonio Griseta, Antonio Lonigro, Angelo Mazzone
  • Built-in self-test method and system
    Publication number: 20070011511
    Abstract: A method for testing a memory device having plural memory elements includes performing a succession of operations including: a) writing a test datum into the memory elements according to a first scanning sequence; b) accessing each memory element according to the first scanning sequence, reading a content thereof, comparing the read content to the test datum, and writing thereinto the test datum complement; c) accessing each memory element according to a second scanning sequence, reading a content thereof, comparing the read content to the test datum complement, and writing thereinto the test datum; d) accessing each memory element according to the second scanning sequence, reading a content thereof, comparing the read content to the test datum, writing thereinto the test datum complement, and reading again the content thereof and comparing the read content to the test datum complement.
    Type: Application
    Filed: May 17, 2006
    Publication date: January 11, 2007
    Applicant: STMicroelectronics S.r.l.
    Inventors: Antonio Griseta, Angelo Mazzone, Luigi Penza
  • ECC for single 4-bits symbol correction of 32 symbols words with 22 maximum row weight matrix
    Publication number: 20070011601
    Abstract: An error correction device is provided. Such error correction device may make use of an error-correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row Weight equal to 22.
    Type: Application
    Filed: May 19, 2006
    Publication date: January 11, 2007
    Inventors: Antonio Griseta, Angelo Mazzone
  • Built-in self test circuit for integrated circuits
    Publication number: 20040107396
    Abstract: A built-in self-test circuit adapted to be embedded in an integrated circuit for testing the integrated circuit, including in particular a collection of addressable elements, for example a semiconductor memory. The BIST circuit comprises a general-purpose data processor programmable for executing a test program for testing the integrated circuit. The BIST circuit comprises an accelerator circuit cooperating with the general-purpose data processor for autonomously conducting operations on the integrated circuit according to the test program. The accelerator circuit comprises configuration means adapted to be loaded with configuration parameters for adapting the accelerator circuit to the specific type of integrated circuit and the specific type of test program.
    Type: Application
    Filed: August 7, 2003
    Publication date: June 3, 2004
    Applicant: STMicroelectronics S.r.l.
    Inventors: Massimiliano Barone, Antonio Griseta