Patents by Inventor Antonio H. Chan

Antonio H. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7242209
    Abstract: A module (236, 236?) containing an integrated testing system (108) that includes one or more measurement engines (200, 202) tightly coupled with a compute engine (208). The one or more measurement engines include at least one stimulus instrument (212) for exciting circuitry of a device-under-test (104) with one or more stimulus signals, and at least one measurement instrument (216) that measures the response of the device-under-test to the stimulus signal(s) and generates measurement data. The compute engine includes computation logic circuitry (800) for determining whether or not the circuitry aboard the device-under-test passes or fails. The integrated testing system further includes a communications engine (204) providing two-way communications between the integrated testing system automated testing equipment (116) and/or a dedicated user interface (140) residing on a host computer (136).
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: July 10, 2007
    Assignee: DFT Microsystems, Inc.
    Inventors: Gordon W. Roberts, Antonio H. Chan, Geoffrey D. Duerden, Mohamed M. Hafed, Sébastien Laberge, Bardia Pishdad, Clarence K. L. Tam
  • Patent number: 6850051
    Abstract: In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay Locked Loop (DLL) and Vernier Delay Line (VDL) techniques. However, these approaches require highly matched elements in order to reduce differential non-linearity timing errors. In an attempt to reduce the requirement on element matching, a component-invariant VDL technique is disclosed that enables the measurement device to be synthesized from an RTL description. The present invention is based on a single-stage VDL structure, which is used to mimic the behavior of a complete VDL. Furthermore, as test time is an important consideration during a production test, a method and system is provided that reduces test time at the expense of additional hardware.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: February 1, 2005
    Assignee: McGill University
    Inventors: Gordon W. Roberts, Antonio H. Chan
  • Publication number: 20030006750
    Abstract: In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay Locked Loop (DLL) and Vernier Delay Line (VDL) techniques. However, these approaches require highly matched elements in order to reduce differential non-linearity timing errors. In an attempt to reduce the requirement on element matching, a component-invariant VDL technique is disclosed that enables the measurement device to be synthesized from an RTL description. The present invention is based on a single-stage VDL structure, which is used to mimic the behavior of a complete VDL. Furthermore, as test time is an important consideration during a production test, a method and system is provided that reduces test time at the expense of additional hardware.
    Type: Application
    Filed: March 26, 2002
    Publication date: January 9, 2003
    Applicant: McGill University
    Inventors: Gordon W. Roberts, Antonio H. Chan