Abstract: Receiver embodiments are disclosed that can process a wide range of transmission bandwidths over a wide range of transmission frequencies and provide reduced converter sampling rates, filter bandwidths, and filter tuning ranges and enhanced signal-to-noise performance. They convert transmission signals with quadrature local oscillator signals whose frequencies are commanded to be a selected transmission frequency when a selected transmission bandwidth is above a predetermined bandwidth threshold and are commanded to be offset from the selected transmission frequency by an intermediate frequency that is at least one half of the selected transmission bandwidth when the selected transmission bandwidth is below the bandwidth threshold.

Abstract: A radio transmission power control circuit includes a radio frequency (rf) downconverter that produces a downconverter output representative of the difference between a first downconverter input based on a transmitted signal of a radio transmitter and a second downconverter input based on a local oscillator signal. A receiver baseband circuit processes the downconverter output to produce an analog power signal representative of the transmitted signal. A digital to analog converter converts the analog power signal to a representative digital power signal. A feedback control circuit produces a transmitter gain control signal to control transmitted signal power so as to minimize the difference between the digital power signal and a power reference signal.

Abstract: A programmable digital divider operates under the control of a division controller to derive a second synthesized frequency based on a first synthesized frequency. The programmable divider divides the first synthesized signal to derive the second synthesized signal. The division amount is an integer, but varies between integer values if necessary to achieve a non-integer average division value. The majority of the noise generated by the frequency synthesizer is generated away from the centerline frequency and is easily filtered by narrowband filter. The frequency synthesizer may optionally be incorporated into a modified phase-locked loop to generate the second synthesized signal. By using a digital divider, instead of a traditional phase-locked loop, these embodiments allow for integration of the frequency synthesizer onto an integrated circuit, thereby lowering cost and improving resistance to noise spurs. This approach is particularly suited to telecommunications applications.

Abstract: Phase-locked loop methods and structures are provided for generating modulated communication signals with nonconstant envelopes. These methods and structures realize the improved communication performance of nonconstant-envelope modulations with the upconversion advantages of phase-locked loops. The structures include transmitters in which a phase-locked loop is augmented with first and second feedforward paths that substantially restore phase and amplitude information to a transmit signal that is generated by a voltage-controlled oscillator of the phase-locked loop. The first feedforward path is configured to realize a path transfer function of s/Kv wherein the voltage-controlled oscillator has a transfer function of Kv/s. The second feedforward path extracts an envelope-correction signal from the modulated intermediate-frequency signal and a variable-gain output amplifier amplifies the transmit signal with a gain that responds to the envelope-correction signal.

Abstract: An apparatus and method for creating an amplifier input waveform based on received phase and amplitude information from an input signal. The apparatus includes a first switch receiving phase information from a primary waveform and a second switch in communication with the first switch and the input. The second switch receives amplitude information from the primary waveform and receives the phase information from the first switch and uses the amplitude information to modulate the phase information. A secondary waveform is thus created for input to the amplifier load matching network. In this way, an amplitude modulated waveform is amplified at high efficiency, enabling application of either all or part of the phase and/or amplitude modulation at the input of the amplifier.

Abstract: A flash EEPROM array architecture including a plurality of pages is provided according to the principles of this invention. Each page of the array is isolated from other pages in the array during reading, programming and erasing of the page. The novel architecture of this invention includes means for erasing through the gate of the flash EEPROM cell.

Abstract: A charge pump circuit is provided comprising a MOS capacitor, a capacitor ("series capacitor") connected in series, a MOSFET diode, and a voltage clamp connected to the common node of the MOS capacitor and the series capacitor. A number of these charge pump circuits may be cascaded to form a multi-stage charge pump circuit. Each charge pump circuit may attain output voltage higher than the oxide breakdown voltage of each individual MOS capacitor. This charge pump circuit can also operate under low voltage power supply conditions.

Abstract: A charge pump circuit is provided comprising a first MOSFET capacitor ("pumping capacitor"), two other MOSFET capacitors ("back-to-back capacitors") connected together with a common junction of the back-to-back capacitor in series with the pumping capacitor, a voltage clamp connected to the common node of all three MOSFET capacitors, and a diode for output of the charge pumped. A number of these charge pump circuits may be cascaded to form a multi-stage charge pump circuit. Each charge pump circuit may attain output voltage higher than the oxide breakdown voltage of each individual MOS capacitor. This charge pump circuit can also operate under low voltage power supply conditions.