Patents by Inventor Antonio Jr. Bambalan Dimaano
Antonio Jr. Bambalan Dimaano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190348387Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Inventors: Yongbo YANG, Antonio Jr. Bambalan DIMAANO, Chun Hong WO
-
Patent number: 10403592Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.Type: GrantFiled: October 6, 2017Date of Patent: September 3, 2019Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Yongbo Yang, Antonio Jr. Bambalan Dimaano, Chun Hong Wo
-
Patent number: 10354934Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: GrantFiled: April 24, 2018Date of Patent: July 16, 2019Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Nathapong Suthiwongsunthorn, Antonio Jr. Bambalan Dimaano, Rui Huang, Hua Hong Tan, Kriangsak Sae Le, Beng Yeung Ho, Nelson Agbisit De Vera, Roel Adeva Robles, Wedanni Linsangan Micla
-
Publication number: 20180240726Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: ApplicationFiled: April 24, 2018Publication date: August 23, 2018Inventors: Nathapong SUTHIWONGSUNTHORN, Antonio Jr. Bambalan DIMAANO, Rui HUANG, Hua Hong TAN, Kriangsak Sae LE, Beng Yeung HO, Nelson Agbisit DE VERA, Roel Adeva ROBLES, Wedanni Linsangan MICLA
-
Patent number: 9978658Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: GrantFiled: November 27, 2016Date of Patent: May 22, 2018Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Nathapong Suthiwongsunthorn, Antonio Jr. Bambalan Dimaano, Rui Huang, Hua Hong Tan, Kriangsak Sae Le, Beng Yeung Ho, Nelson Agbisit De Vera, Roel Adeva Robles, Wedanni Linsangan Micla
-
Patent number: 9960130Abstract: Devices and methods for forming a device are disclosed. The device includes a contact region disposed over a last interconnect level of the device. The device includes a final passivation layer having at least an opening which at least partially exposes a top surface of the contact region and a buffer layer disposed at least over a first exposed portion of the top surface of the contact region. When an electrically conductive interconnection couples to the contact region, the buffer layer absorbs a portion of a force exerted to form an interconnection between the electrically conductive interconnection and the contact region.Type: GrantFiled: February 6, 2015Date of Patent: May 1, 2018Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Rui Huang, Chun Hong Wo, Antonio Jr. Bambalan DiMaano
-
Publication number: 20180033759Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.Type: ApplicationFiled: October 6, 2017Publication date: February 1, 2018Inventors: Yongbo YANG, Antonio Jr. Bambalan DIMAANO, Chun Hong WO
-
Patent number: 9786625Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.Type: GrantFiled: July 20, 2015Date of Patent: October 10, 2017Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Yongbo Yang, Antonio Jr. Bambalan Dimaano, Chun Hong Wo
-
Publication number: 20170077007Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: ApplicationFiled: November 27, 2016Publication date: March 16, 2017Inventors: Nathapong SUTHIWONGSUNTHORN, Antonio Jr. Bambalan DIMAANO, Rui HUANG, Hua Hong TAN, Kriangsak Sae LE, Beng Yeung HO, Nelson Agbisit DE VERA, Roel Adeva ROBLES, Wedanni Linsangan MICLA
-
Patent number: 9508623Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: GrantFiled: June 5, 2015Date of Patent: November 29, 2016Assignee: UTAC HEADQUARTERS PTE. LTD.Inventors: Nathapong Suthiwongsunthorn, Antonio Jr. Bambalan Dimaano, Rui Huang, Hua Hong Tan, Kriangsak Sae Le, Beng Yeung Ho, Nelson Agbisit De Vera, Roel Adeva Robles, Wedanni Linsangan Micla
-
Publication number: 20160233179Abstract: Devices and methods for forming a device are disclosed. The device includes a contact region disposed over a last interconnect level of the device. The device includes a final passivation layer having at least an opening which at least partially exposes a top surface of the contact region and a buffer layer disposed at least over a first exposed portion of the top surface of the contact region. When an electrically conductive interconnection couples to the contact region, the buffer layer absorbs a portion of a force exerted to form an interconnection between the electrically conductive interconnection and the contact region.Type: ApplicationFiled: February 6, 2015Publication date: August 11, 2016Inventors: Rui HUANG, Chun Hong WO, Antonio Jr. Bambalan DIMAANO
-
Publication number: 20150357256Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.Type: ApplicationFiled: June 5, 2015Publication date: December 10, 2015Inventors: Nathapong SUTHIWONGSUNTHORN, Antonio Jr. Bambalan DIMAANO, Rui HUANG, Hua Hong TAN, Kriangsak Sae LE, Beng Yeung HO, Nelson Agbisit DE VERA, Roel Adeva ROBLES, Wedanni Linsangan MICLA
-
Publication number: 20150325511Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Inventors: Yongbo YANG, Antonio Jr. Bambalan DIMAANO, Chun Hong WO
-
Patent number: 9087777Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.Type: GrantFiled: March 14, 2013Date of Patent: July 21, 2015Assignee: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Yongbo Yang, Antonio Jr. Bambalan Dimaano, Chun Hong Wo
-
Publication number: 20140264789Abstract: Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: UNITED TEST AND ASSEMBLY CENTER LTD.Inventors: Yongbo Yang, Antonio Jr. Bambalan Dimaano, Chun Hong Wo