Abstract: Techniques are provided to remove the growth of colloidal silica deposits on surfaces of high aspect ratio structures during silicon nitride etch steps. A high selectivity overetch step is used to remove the deposited colloidal silica. The disclosed techniques include the use of phosphoric acid to remove silicon nitride from structures having silicon nitride formed in narrow gap or trench structures having high aspect ratios in which formation of colloidal silica deposits on a surface of the narrow gap or trench through a hydrolysis reaction occurs. A second etch step is used in which the hydrolysis reaction which formed the colloidal silica deposits is reversible, and with the now lower concentration of silica in the nearby phosphoric acid due to the depletion of the silicon nitride, the equilibrium drives the reaction in the reverse direction, dissolving the deposited silica back into solution.

Abstract: A technique to inhibit the growth of colloidal silica deposits on surfaces treated in phosphoric acid is described. In one embodiment, the disclosed techniques include the use of a colloidal silica growth inhibitor as an additive to a phosphoric acid solution utilized for a silicon nitride etch. In some embodiments, the additive may have chemistry that may contain strong anionic groups. A method and apparatus is provided that monitors the silica concentration and/or the colloidal silica growth inhibitor concentration in the phosphoric acid solution during processing and adjusts the amount of those components as needed. Techniques are provided for a method and apparatus to control the additive concentration to be used as well as the silica concentration in the phosphoric acid solution. The techniques described herein provide a high selectivity etch of silicon nitride towards silicon dioxide without the growth of colloidal silica deposits on the exposed surfaces.

Abstract: Techniques are provided to remove the growth of colloidal silica deposits on surfaces of high aspect ratio structures during silicon nitride etch steps. A high selectivity overetch step is used to remove the deposited colloidal silica. The disclosed techniques include the use of phosphoric acid to remove silicon nitride from structures having silicon nitride formed in narrow gap or trench structures having high aspect ratios in which formation of colloidal silica deposits on a surface of the narrow gap or trench through a hydrolysis reaction occurs. A second etch step is used in which the hydrolysis reaction which formed the colloidal silica deposits is reversible, and with the now lower concentration of silica in the nearby phosphoric acid due to the depletion of the silicon nitride, the equilibrium drives the reaction in the reverse direction, dissolving the deposited silica back into solution.

Abstract: Techniques are provided to remove the growth of colloidal silica deposits on surfaces of high aspect ratio structures during silicon nitride etch steps. A high selectivity overetch step is used to remove the deposited colloidal silica. The disclosed techniques include the use of phosphoric acid to remove silicon nitride from structures having silicon nitride formed in narrow gap or trench structures having high aspect ratios in which formation of colloidal silica deposits on a surface of the narrow gap or trench through a hydrolysis reaction occurs. A second etch step is used in which the hydrolysis reaction which formed the colloidal silica deposits is reversible, and with the now lower concentration of silica in the nearby phosphoric acid due to the depletion of the silicon nitride, the equilibrium drives the reaction in the reverse direction, dissolving the deposited silica back into solution.

Abstract: A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (?). This results in a lower parasitic capacitance at the body contact region.

Abstract: A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (?). This results in a lower parasitic capacitance at the body contact region.

Abstract: A shallow trench isolation structure is formed in a semiconductor substrate adjacent to an active semiconductor region. A selective self-assembling oxygen barrier layer is formed on the surface of the shallow trench isolation structure that includes a dielectric oxide material. The formation of the selective self-assembling oxygen barrier layer is selective in that it is not formed on the surface the active semiconductor region having a semiconductor surface. The selective self-assembling oxygen barrier layer is a self-assembled monomer layer of a chemical which is a derivative of alkylsilanes including at least one alkylene moiety. The silicon containing portion of the chemical forms polysiloxane, which is bonded to surface silanol groups via Si—O—Si bonds. The monolayer of the chemical is the selective self-assembling oxygen barrier layer that prevents diffusion of oxygen to a high dielectric constant material layer that is subsequently deposited as a gate dielectric.

Abstract: A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (?). This results in a lower parasitic capacitance at the body contact region.

Abstract: A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.

Abstract: A body contacted semiconductor-on-insulator (SOI) metal gate containing transistor that has a reduced parasitic gate capacitance is provided in which a metal portion of a gate stack is removed over the body contact region and a silicon-containing material is formed that contacts the gate dielectric in the body contact region of an SOI substrate. This causes an increase of the effective gate dielectric thickness on the body contact region by greater than 5 angstroms (?). This results in a lower parasitic capacitance at the body contact region.

Abstract: There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.

Abstract: A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.

Abstract: CMOS gate dielectric made of high-k metal silicates by reaction of metal with silicon dioxide at the silicon surface. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Abstract: A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly of the dielectric layer. A silicon-germanium layer is formed outwardly of the metal layer. A first portion of the silicon-germanium layer is removed to expose a first portion of the metal layer, with a second portion of the silicon-germanium layer remaining over a second portion of the metal layer. A silicon-germanium metal compound layer is formed from the second portion of the silicon-germanium layer and the second portion of the metal layer. A first gate electrode comprising the first portion of the metal layer is formed. A second gate electrode comprising the silicon-germanium metal compound layer is formed.

Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

Abstract: CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.

Abstract: A method for improving high-? gate dielectric film (104) properties. The high-? film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.

Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

Abstract: A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.

Abstract: A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.