Abstract: In the present invention, an improved synchronous PLA circuit is disclosed. The PLA circuit is responsive to a single clock cycle. The PLA circuit has no internal or output glitches. Further, the PLA circuit uses less power since there are no internal or output glitches. The PLA circuit requires less area since metal lines do not have to carry as much power and do not have to be as wide as the prior art PLA circuits. Since less power is used, long term reliability is improved due to reduced heating stress and reduced current density stress (metal electromigration, etc.). The PLA circuit consists of two logic arrays and four dummy signal delay lines. When a clock signal gates the input signals into the logic array, it also simultaneously generates a dummy signal. The dummy signal propagates through adjacent dummy signal delay lines that parallel each logic array dimension and match the longest or worst case, delay through the logic array.