Abstract: A DC-to-DC converter controller configured to generate phase control signals to control a plurality of power stages of a DC-to-DC converter where each power stage includes two phases. The DC-to-DC converter controller is configured to generate the phase control signals in a manner which (a) balances magnitude of current processed among the two phases of each power stage and (b) balances magnitude of current processed among the plurality of power stages.

Abstract: A dead time detector detects when a dead time occurs in a switching regulator comprising a high-side switch and a low-side switch and generates an output signal based on a duration of the dead time. A first circuit generates a first turn-on signal to turn on the high-side switch and a first turn-off signal to turn off the low-side switch based on the output signal in response to a first edge of a pulse width modulated pulse. A second circuit generates a second turn-on signal to turn on the low-side switch and a second turn-off signal to turn off the high-side switch based on the output signal in response to a second edge of the pulse width modulated pulse. A controller generates drive signals to drive the high-side and low-side switches based on the first and second turn-on and turn-off signals.

Abstract: The present invention relates to a voltage converter based on a switching regulator, and more particularly, to systems, devices and methods of dynamically controlling an output of the voltage converter to rapidly transition between different power supply voltages as required in many electronic devices. The switching regulator generates an output supply voltage that tracks a voltage originally provided by an internal DAC. During the supply voltage variation, a step control signal is provided to introduce a supplemental voltage step into the reference voltage before the reference voltage is used to generate the output supply voltage. The switching regulator is thereby overdriven under this supplemental voltage step, enhancing the slew rate and the settling time of the output supply voltage to meet stringent requirements imposed by many electronic devices.

Abstract: Various embodiments of the invention provide for a double measurement technique to enable auto-calibration of a switching regulator. In certain embodiments, calibration is performed using a digital conversion circuit that adjusts an internal slope of an on-time generator by adjusting the peak value of a ramp to a desired peak voltage value. Auto-calibration allows for an optimal dynamic response across the entire switching frequency range of the switching regulator even in noisy environments.

Abstract: Various embodiments of the invention provide extend the switching frequency range of DC/DC multiphase switching regulators in order to overcome prior art frequency limitations in the number of available phases, for example, in low input to output ratio applications. In certain embodiments, this is accomplished by enabling partial overlap between multiple phases using asynchronous logic. The invention is easily scalable without introducing significant silicon area penalties.

Abstract: A dead time detector detects when a dead time occurs in a switching regulator comprising a high-side switch and a low-side switch and generates an output signal based on a duration of the dead time. A first circuit generates a first turn-on signal to turn on the high-side switch and a first turn-off signal to turn off the low-side switch based on the output signal in response to a first edge of a pulse width modulated pulse. A second circuit generates a second turn-on signal to turn on the low-side switch and a second turn-off signal to turn off the high-side switch based on the output signal in response to a second edge of the pulse width modulated pulse. A controller generates drive signals to drive the high-side and low-side switches based on the first and second turn-on and turn-off signals.

Abstract: Various embodiments of the invention provide extend the switching frequency range of DC/DC multiphase switching regulators in order to overcome prior art frequency limitations in the number of available phases, for example, in low input to output ratio applications. In certain embodiments, this is accomplished by enabling partial overlap between multiple phases using asynchronous logic. The invention is easily scalable without introducing significant silicon area penalties.

Abstract: A method and a circuit for minimizing glitches in phase-locked loops is presented. The circuit includes an input terminal connected to an input of a phase detector; a series of a charge pump generator, a filter and a voltage controlled oscillator connected downstream of the phase detector; and a frequency divider feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector. The circuit provides for the inclusion of a compensation circuit connected between the charge pump generator and the filter to absorb an amount of the charge passed therethrough. This compensation circuit includes a storage element connected in series to two switches. The first switch is coupled to and controlled by an output of the charge pump and the second switch is coupled to and controlled by an output of a phase detector.

Abstract: A method and a circuit for minimizing glitches in phase-locked loops is presented. The circuit includes an input terminal connected to an input of a phase detector; a series of a charge pump generator, a filter and a voltage controlled oscillator connected downstream of the phase detector; and a frequency divider feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector. The circuit provides for the inclusion of a compensation circuit connected between the charge pump generator and the filter to absorb an amount of the charge passed therethrough. This compensation circuit includes a storage element connected in series to two switches. The first switch is coupled to and controlled by an output of the charge pump and the second switch is coupled to and controlled by an output of a phase detector.

Abstract: A low noise adaptive bias circuit is provided for a low noise bipolar junction input transistor having an emitter degeneration inductance, of an integrated high frequency functional circuit driven by the collector current of the input transistor. The bias circuit includes a shunt line connecting the base node of the input transistor to a first supply node of opposite sign of that of a second supply node to which is coupled, through the degeneration inductance, to the emitter of the input transistor. The shunt line includes a bias current generator dependent, in an inversely proportional manner, on the current gain of the input transistor, and a resistance dependent, in a directly proportional manner, on the current gain of the input transistor.

Abstract: An electronic device smoothes a charge current peak in RLC output stages of switching step-up regulators, which stages include an input terminal and an output terminal with an inductance and a parasitic resistance in series therebetween, the latter corresponding to the series parasitic resistance of the inductance, and a capacitor connected between the output terminal and a ground. The device comprises a parallel of a resistor and a controlled switch connected between the inductance and the output terminal of the stage upstream of the capacitor. Advantageously, the switch would only be open during the charge transient of the capacitor.

Abstract: A method of controlling the charging of a bootstrap capacitance incorporated into a switching regulator of a power transistor includes the steps of comparing, at each switching cycle, the voltage value at the bootstrap capacitance and a predetermined threshold voltage, to change the mode of operation of the regulator following said comparison. More particularly, the control on the transistor is taken off the regulator when the voltage at the bootstrap capacitance is lower than the threshold voltage, while the transistor is forced into the "on" state through a full cycle. In this way, the minimum current to operate the regulator can be minimised.

Abstract: A synchronization circuit for electronic devices and components, being of the type which includes an internal synchronization signal generator and an input/output terminal whereat an external synchronization signal can be received. The synchronization circuit further includes a comparator for receiving both synchronization signals and having a control output for supplying a terminal with the signal corresponding to the master/slave mode of operation of the synchronization circuit. A method of generating and supplying a synchronization signal to a plurality of electronic devices being operated as slave devices to a synchronization circuit acting as the master device is also provided.

Abstract: A translator circuit for a drive circuit of a power transistor connected to an electric load. The translator circuit includes a first current generator placed between a supply voltage reference and an input terminal of the drive circuit, a controlled switch placed between the input terminal and a ground reference, and a second current generator interposed between the controlled switch and the ground reference. The translator circuit further includes a circuit leg in the form of a current mirror connected in parallel with the second current generator. The translator circuit avoids phenomena of false switching.

Abstract: A driver circuit is for turning on at least one power MOS transistor having a diode connected thereto. The driver circuit preferably includes a smart driver circuit portion for increasing a drive current to the power MOS transistor responsive to turning on of the diode. The smart driver circuit may include a comparator having one input connected to the diode and a second input connected to a threshold signal indicative of the turning on of the diode. The smart driver circuit may also comprise: a first current source for supplying a first drive current; a second current source for supplying a second drive current; and a switch for connecting the second current source to the power MOS transistor responsive to the comparator. The smart driver circuit may further include a turn off circuit for turning off the increased drive current a predetermined time after turning on same, such as before turning off the first current.

Abstract: Switching and propagation delays in generating a PWM control signal by a circuit that generally includes an error amplifier, a sawtooth oscillator and a comparator for comparing the error signal with the sawtooth signal, is compensated by generating a second sawtooth signal synchronous with the master sawtooth signal but having a reduced discharge time and by applying the second synchronous sawtooth signal to the respective input of the PWM comparator.