Abstract: A device for depositing at least one especially thin layer onto at least one substrate includes a process chamber housed in a reactor housing and includes a movable susceptor which carries the at least one substrate. A plurality of gas feed lines run into said process chamber and feed different process gases which comprise layer-forming components. Said process gases can be fed to the process chamber in subsequent process steps, thereby depositing the layer-forming components onto the substrate. In order to increase throughput, the process chamber is provided with a plurality of separate deposition chambers into which different gas feed lines run, thereby feeding individual gas compositions. The substrate can be fed to said chambers one after the other by moving the susceptor and depositing different layers or layer components.

Abstract: A device for depositing at least one especially thin layer onto at least one substrate includes a process chamber housed in a reactor housing and includes a movable susceptor which carries the at least one substrate. A plurality of gas feed lines run into said process chamber and feed different process gases which comprise layer-forming components. Said process gases can be fed to the process chamber in subsequent process steps, thereby depositing the layer-forming components onto the substrate. In order to increase throughput, the process chamber is provided with a plurality of separate deposition chambers into which different gas feed lines run, thereby feeding individual gas compositions. The substrate can be fed to said chambers one after the other by moving the susceptor and depositing different layers or layer components.

Abstract: In a method for manufacturing a field effect transistor, a semiconductor layer sequence is grown that has a channel layer (2), a barrier layer (3) and a highly doped InGaAs layer (6) suitable for low-impedance contacting to a metal contact. A passivation layer (8) of dielectric is applied and is structured for the region lying between source, gate and drain. An auxiliary layer (10) is applied by vapor-deposition in a very flat incident angle such that the gate region remains free. The semiconductor layers are etched out in the region of the gate down onto the barrier in a plurality of RIE etching processes. The auxiliary layer is removed, spacers are produced at the sidewalls of the passivation layer, a refractory metallization is deposited surface-wide and etched back in planarizing fashion, so that separate contacts for source, gate and drain derive. Finally, the terminal metallization is applied.