Patents by Inventor Antonio Pelella
Antonio Pelella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11682452Abstract: Aspects of the invention include a first pull-down device and a second pull-down device, wherein a first drain terminal is connected to a second source terminal, and wherein a first gate terminal is connected to a true read local bitline, wherein a second drain terminal is connected to a compliment read local bit line, and wherein a second gate terminal is connected to a true write global bitline, a third pull-down device and a fourth pull-down device, wherein a third source terminal is connected to the voltage supply, wherein a third drain terminal is connected to a fourth source terminal, and wherein a third gate terminal is connected to the compliment read local bitline, and wherein a fourth drain terminal is connected to the true read local bitline, and wherein a fourth gate terminal is connected to a compliment write global bit line.Type: GrantFiled: September 21, 2021Date of Patent: June 20, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Antonio Pelella, Dongho Lee, Genadi Tverskoy, Zhiying Chen, Brian James Yavoich
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Publication number: 20230086799Abstract: Aspects of the invention include a first pull-down device and a second pull-down device, wherein a first drain terminal is connected to a second source terminal, and wherein a first gate terminal is connected to a true read local bitline, wherein a second drain terminal is connected to a compliment read local bit line, and wherein a second gate terminal is connected to a true write global bitline, a third pull-down device and a fourth pull-down device, wherein a third source terminal is connected to the voltage supply, wherein a third drain terminal is connected to a fourth source terminal, and wherein a third gate terminal is connected to the compliment read local bitline, and wherein a fourth drain terminal is connected to the true read local bitline, and wherein a fourth gate terminal is connected to a compliment write global bit line.Type: ApplicationFiled: September 21, 2021Publication date: March 23, 2023Inventors: Antonio PELELLA, Dongho LEE, Genadi TVERSKOY, Zhiying CHEN, Brian James YAVOICH
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Publication number: 20110317478Abstract: An improved method for performing a write through operation during a write operation of a SRAM cell (10) of a SRAM array (1) is disclosed. The method comprises suppressing a false write through data propagation at an output node (C, F) of the SRAM array (1) in case of a failure causing transition at a first node (t) or a second node (c) of the SRAM cell (10) by using information about the input data (data, data_b) to be written in the SRAM cell (10) and read data propagation paths to retain the output node (C, F) after a global bit line (gb_t, gb_c) at a precharge level independently from a logical level of the global bit line (gb_t, gb_c), if a corresponding node (c, t) of the SRAM cell (10) is performing the failure causing transition based on input data (data, data_b) to be written in the SRAM cell (10).Type: ApplicationFiled: June 1, 2011Publication date: December 29, 2011Applicant: International Business Machines CorporationInventors: Yuen H. Chan, Michael Kugel, Antonio Pelella, Tobias Werner
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Publication number: 20080056052Abstract: A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.Type: ApplicationFiled: November 1, 2007Publication date: March 6, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuen Chan, Ryan Freese, Antonio Pelella, Arthur Tuminaro
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Publication number: 20070058421Abstract: A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ck1), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.Type: ApplicationFiled: October 30, 2006Publication date: March 15, 2007Inventors: Yuen Chan, Ryan Freese, Antonio Pelella, Uma Srinivasan, Arthur Tuminaro, Jatinder Wadhwa
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Patent number: 7170799Abstract: A CMOS static random access memory (SRAM) and a bit select for the SRAM. The bit select includes a dual single-ended sense receiving a difference signal on a bit line pair and selectively sensing signals developing on each bit line independently of the other. Single ended outputs from the dual-ended sense are provided to an output driver. The output driver provides a pair of selectively-complementary output signals.Type: GrantFiled: February 10, 2005Date of Patent: January 30, 2007Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Timothy J. Charest, Rajiv V. Joshi, Antonio Pelella
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Publication number: 20060176732Abstract: A CMOS static random access memory (SRAM) and a bit select for the SRAM. The bit select includes a dual single-ended sense receiving a difference signal on a bit line pair and selectively sensing signals developing on each bit line independently of the other. Single ended outputs from the dual-ended sense are provided to an output driver. The output driver provides a pair of selectively-complementary output signals.Type: ApplicationFiled: February 10, 2005Publication date: August 10, 2006Inventors: Yuen Chan, Timothy Charest, Rajiv Joshi, Antonio Pelella
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Publication number: 20060176728Abstract: Local bit line pairs in a domino SRAM include an amplifier to amplify the voltage differential across the bit lines during a read operation if a cell in the local group of cells has been identified as a slow to read cell. The amplifier includes a transistor switch that is turned on by a timing pulse during the read operation, but only if the Array Built In Self-Test (ABIST) has detected a slow to read cell in the local group. If there is no slow cell, the amplifier is not activated, and the domino read operation is carried out. The amplifier can be used globally across the SRAM or selectively in certain sub-arrays.Type: ApplicationFiled: February 9, 2005Publication date: August 10, 2006Applicant: International Business Machines CorporationInventor: Antonio Pelella
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Publication number: 20060176730Abstract: A domino SRAM array restore pulse generation system launches the word decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activation by releasing the reset signal (with the earliest arriving array clock, ckl), while guaranteeing almost perfect tracking with the bit decode system. This allows for the widest possible write window; earliest release of the pre-charge in the global column select, and resetting only after the bit decode system is deactivated.Type: ApplicationFiled: February 9, 2005Publication date: August 10, 2006Applicant: International Business Machines CorporationInventors: Yuen Chan, Ryan Freese, Antonio Pelella, Uma Srinivasan, Arthur Tuminaro, Jatinder Wadhwa
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Publication number: 20060179375Abstract: A programmable delay circuit that delays the C2 clock signal by a variable amount that allows the output from the L1 latch to be captured even when there is a large delta between the L1 latch and its L2 latch. This allows the C2 signal to be adjusted within the system dependent upon the amount of cycle steal is needed. The C2 clock delay is inhibited during scan operation to prevent glitches and the trailing edge of the delayed C2 is controlled to maintain a constant C2 duty cycle.Type: ApplicationFiled: February 9, 2005Publication date: August 10, 2006Applicant: International Business Machines CorporationInventors: Yuen Chan, Ryan Freese, Antonio Pelella
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Publication number: 20060176729Abstract: A domino SRAM is provided with active pull-up PFET devices that overwhelm “slow to write but very fast to read” cells and allow the cells to recover from timing mismatch situations. This approach allows the traditional “bit select” clamp to actively control the “local select” through “wired-or” PFET pull-up transistors.Type: ApplicationFiled: February 9, 2005Publication date: August 10, 2006Applicant: International Business Machines CorporationInventors: Yuen Chan, Ryan Freese, Antonio Pelella, Arthur Tuminaro
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Publication number: 20060176753Abstract: A domino SRAM global bit select circuit provides an interface between dual global read and write bit line pairs to a “local bit select” circuit.Type: ApplicationFiled: February 9, 2005Publication date: August 10, 2006Applicant: International Business Machines CorporationInventors: Yuen Chan, Ryan Freese, Antonio Pelella, Arthur Tuminaro
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Publication number: 20050254285Abstract: A late select circuit topology has pseudo-static circuits that provide fast dynamic circuit operation without the use of dynamic clock timing signals. An output from a selected set is enabled by the conjunction of bit line pulse and set select signal.Type: ApplicationFiled: May 12, 2004Publication date: November 17, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuen Chan, Timothy Charest, Antonio Pelella, John Rawlins
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Publication number: 20050253639Abstract: A pulse to static converter for SRAM in which the converter latch is comprised of two cross-coupled, complementary, FET pairs. The FETs of each pair are coupled drain to drain between a positive voltage source and ground. The output state of SRAM sense amplifier is coupled as an input to the grates of one FET pair and the state established by this input is latched via the cross coupling with the other FET pair.Type: ApplicationFiled: May 12, 2004Publication date: November 17, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuen Chan, Antonio Pelella, Jatinder Wadhwa, Otto Wagner