Abstract: Programmable impedance elements structures, devices and methods are disclosed. Methods can include: forming a first electrode layer within an electrode opening that extends through a cap layer; planarizing to expose a top of the cap layer; cleaning the exposed top surface of the cap layer to remove residual species from previous process steps. Additional methods can include forming at least a base ion conductor layer having an active metal formed therein that may ion conduct within the ion conductor layer; and forming an inhibitor material that mitigates agglomeration of the active metal within the base ion conductor layer as compared to the active metal alone. Programmable impedance elements and/or devices can have switching material and electrodes parallel to both bottoms and sides of a cell opening formed in a cell dielectric. Other embodiments can include an ion conductor layer having an alloy of an active metal, or two ion conductor layers in contact with an active electrode.

Abstract: A method of forming a conductive bridging memory cell can include forming an active electrode layer above a barrier layer formed on a lower conductive layer; forming at least one ion conductor layer over an active electrode layer; incorporating conductive ions into the ion conductor layer to create a switch memory layer that changes impedance in response to an electric field; and the active electrode layer is a source of conductive ions for the ion conductor, and the barrier layer substantially prevents a movement of conductive ions therethrough.

Abstract: A method can include forming at least one memory layer over a first electrode, the memory layer having at least one element formed therein that oxidizes in the presence of an electric field to form conductive paths within the memory layer; and forming an inhibiting layer within the memory layer that increases an oxidation energy for the at least one element, as compared to the oxidation energy for the at least one element in the memory layer without the inhibiting layer.

Abstract: A memory device can include a plurality of memory elements, each including first electrode having a surrounding first electrode side surface in a lateral direction; a memory material surrounding the first electrode side surface in the lateral direction, the memory material being programmable between at least two different impedance states in response to electric fields; and a second electrode formed around the memory material in the lateral direction.

Abstract: A programmable impedance memory device structure can include a multi-layer variable impedance memory element formed on a planar surface of a first barrier layer, the multi-layer variable impedance memory element comprising a plurality of layers substantially parallel to the planar surface, including a memory material layer in contact with the planar surface, the first barrier layer being formed above a first insulating layer; and a second barrier layer formed over the memory element having a top surface substantially parallel with the planar surface. The first and second barrier layers can have lower mobility rates for at least one element within the memory material layer than the first insulating layer, and the memory material layer can be programmable by application of an electrical field between at least two different impedance states.

Abstract: A memory device can include at least one cathode formed in first opening of a first insulating layer; at least one anode formed in a second opening of second insulating layer, the second insulating layer being a different vertical layer than the first insulating layer; and a memory layer comprising an ion conductor layer extending laterally between the at least one anode and cathode on the first insulating layer, the ion conductor layer having a thickness in the vertical direction less than a depth of the first opening.

Abstract: A method can include forming at least one memory layer over a first electrode, the memory layer having at least one element formed therein that oxidizes in the presence of an electric field to form conductive paths within the memory layer; and forming an inhibiting layer within the memory layer that increases an oxidation energy for the at least one element, as compared to the oxidation energy for the at least one element in the memory layer without the inhibiting layer.

Abstract: A memory element can include a memory layer formed between two electrodes; at least one element within the memory layer that is oxidizable in the presence of an electric field applied across the electrodes; and an inhibitor material incorporated into at least a portion of the memory layer that decreases an oxidation rate of the at least one element within the memory layer with respect to the memory layer alone. Methods of forming such a memory element are also disclosed.

Abstract: A conductive bridging memory cell may include an ion conductor layer formed over an active electrode that is a source of conductive ions for the ion conductor; a conductive layer; and a barrier layer formed below the active layer and in contact with the conductive, the barrier layer substantially preventing a movement of conductive ions therethrough.

Abstract: A memory element can include a memory layer formed between two electrodes; at least one element within the memory layer that is oxidizable in the presence of an electric field applied across the electrodes; and an inhibitor material incorporated into at least a portion of the memory layer that decreases an oxidation rate of the at least one element within the memory layer with respect to the memory layer alone. Methods of forming such a memory element are also disclosed.

Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.

Abstract: A tool for manufacturing molecular electronic devices having a coating unit contained in a controlled ambient environment. The coating unit is coupled to a source of active device molecules in solution. The coating unit is configured to apply a selected quantity of the solution to a surface of a substrate and the process tool processes the coated substrate in conditions that cause the active device molecules to attach to active areas of the substrate.

Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.

Abstract: Molecular memories, i.e., memories that incorporate molecules for charge storage, are disclosed. Molecular memory cells, molecular memory arrays, and electronic devices including molecular memory are also disclosed, as are processing systems and methods for manufacturing molecular memories. Methods of manufacturing molecular memories that enable semiconductor devices and interconnections to be manufactured monolithically with molecular memory are also disclosed.

Abstract: A molecular memory element comprising a switching device; at least a first bit line and a first word line coupled to said switching device; and an array of storage locations, each coupled to a bit line and a word line, said elements comprising a first electrode with storage molecules comprising redox active molecules, and said array comprising a second electrode.

Abstract: The amount of laser energy absorbed by a dielectric material during laser fuse blow is increased by changing the angle at which the laser is transmitted. An increased angle of incidence will result in increased energy absorption at the top and edge of the device. This technique may eliminate the need for second pass fuse blow.

Abstract: A waveguide structure is directly extruded onto a surface from a nozzle placed a predetermined distance above the surface and which is moved relative to the surface, preferably by means of a translation table. The predetermined distance is preferably maintained constant and the speed of relative motion regulated to achieve a uniform degree of molecular orientation within the extruded material, thus maintaining a sufficiently uniform refractive index along the axis of the waveguide. Partitions within the nozzle allow the formation of a layered waveguide or the simultaneous formation of concentric cladding or protective layers. The waveguides are advantageously formed as a curtain which is later patterned, by direct writing on the surface or between chips mounted on an electronic module.

Abstract: Disclosed is an optical signal distribution system. The system comprises an electronic substrate, at least one optical component and at least one optical waveguide on but distinct from the electronic substrate for carrying an optical signal to or from the optical component.

Abstract: A method is disclosed of forming a semiconductor device including performing a dry plasma etch at one major surface of a monocrystalline silicon substrate to form a sloped lateral wall lying in a selected crystallographic plane intersecting one major surface. The oriented sloped lateral wall is formed during plasma etching by introducing into contact with said major surface at unprotected locations a chlorofluorocarbon gas and employing during etching a pressure of at least 6.67 Pa and a radio frequency power density of less than 3 watts per square centimeter.