Abstract: A dynamic decode circuit for decoding a plurality of input signals to produce a positive output pulse one gate delay following a clock signal, wherein the output pulse indicates the plurality of signals were in a predetermined state, wherein the output pulse is active during an evaluation phase of a clock cycle and not active during a precharge phase of the clock cycle, wherein precharge is performed by nfet transistors.

Abstract: A dynamic decode circuit for decoding a plurality of input signals to produce a positive output pulse one gate delay following a clock signal, wherein the output pulse indicates the plurality of signals were all positive, wherein the output pulse is active during an evaluation phase of a clock cycle and not active during a precharge phase of the clock cycle, wherein precharge is performed by nfet transistors.

Abstract: A plurality of dynamic decode circuits for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the plurality of dynamic decode circuits sharing a conditioned node.

Abstract: A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.

Abstract: A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

Abstract: A plurality of dynamic decode circuits for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the plurality of dynamic decode circuits sharing a conditioned node.

Abstract: A method for a dynamic decode circuit to decode a plurality of input signals, the dynamic decode circuit comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises precharge circuits that consist of two serially connected transistors, that utilize an evaluate clock and a delayed evaluate clock, that delay the start of a precharge phase for a predetermined period after the end of an evaluation phase.

Abstract: A method for decoding a plurality of input signals in a plurality of dynamic decode circuits, each dynamic decode circuit sharing a conditioned node and comprising a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

Abstract: A dynamic decode circuit for decoding a plurality of input signals comprises a decoder that decodes the plurality of input signals to produce a result at a first node, the result is propagated to a second node while an evaluation clock is active by a pair of serially connected transistors consisting of a transistor receiving an evaluation clock at its gate and a transistor receiving the first node at its gate, the interconnection of the pair of serially connected transistors is precharged when the evaluation clock is inactive to provide a delay between the end of the active evaluation clock and the beginning of the precharge.

Abstract: A GRA cell used in logic for digital systems has a master/slave latch circuit which has a L1 master latch circuit and an L2 slave latch circuit. The L1 master latch circuit having a first cross-coupled portion and a complementary write circuit coupled to the slave latch and having scan-in port coupled to pass a scan-in signal to an L1 pass gate NFET transistor. An A.sub.-- Clock terminal port is connected to the L1 pass gate NFET transistor. The L2 slave latch's input is an output from the L1 master latch circuit. This L2 slave latch includes a second cross-coupled portion and a complementary write circuit. The L2 slave latch circuit is coupled to receive a signal resulting from the scan-in signal via said L1 latch circuit and an L2 pass gate NFET transistor for testing of said master/slave latch circuit. A B.sub.-- Clock terminal is connected to the L2 pass gate NFET transistor. This allows testing to be used with the single NFET pass gate transistors for each latch.

Abstract: A GRA cell used in logic for digital systems has a master/slave latch circuit which has a L1 master latch circuit and an L2 slave latch circuit. The L1 master latch circuit having a first cross-coupled portion and a complementary write circuit coupled to the slave latch and having scan-in port coupled to pass a scan-in signal to an L1 pass gate NFET transistor. An A.sub.-- Clock terminal port is connected to the L1 pass gate NFET transistor. The L2 slave latch's input is an output from the L1 master latch circuit. This L2 slave latch includes a second cross-coupled portion and a complementary write circuit. The L2 slave latch circuit is coupled to receive a signal resulting from the scan-in signal via said L1 latch circuit and an L2 pass gate NFET transistor for testing of said master/slave latch circuit. A B.sub.-- Clock terminal is connected to the L2 pass gate NFET transistor. This allows testing to be used with the single NFET pass gate transistors for each latch.

Abstract: A pipelined set-associative cache data READ/WRITE access circuit advancing the processing performance speeds in microprocessor memories. It provides an apparatus and method to obtain quick access to multi-way cache memory associates for both READ and WRITE operations satisfying the required increased memory access performance speeds for modern microprocessor utilizations. Special methodology is employed to minimize the number of pathways and the pathway through-time of the longest time critical path even with a provision of array built in self test (ABIST) capability.