Patents by Inventor Antonio Rosario Taloban

Antonio Rosario Taloban has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Plating interconnect for silicon chip
    Patent number: 10755940
    Abstract: A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: August 25, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jerard Canuto Malado, Antonio Rosario Taloban, Jr.
  • PLATING INTERCONNECT FOR SILICON CHIP
    Publication number: 20200027737
    Abstract: A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Jerard Canuto Malado, Antonio Rosario Taloban, JR.
  • Plating interconnect for silicon chip
    Patent number: 10504736
    Abstract: A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 10, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jerard Canuto Malado, Antonio Rosario Taloban, Jr.
  • Die detection and reference die wafermap alignment
    Publication number: 20080188016
    Abstract: One embodiment of the present invention includes a method for aligning a wafermap with a semiconductor wafer. The method may comprise assigning a location code to each of a plurality of dies on the wafermap. Each of the plurality of dies on the wafermap can correspond to each of a plurality of dies on the semiconductor wafer. The method may also comprise scanning an approximate location of a reference die on the semiconductor wafer with a die detection sensor based on the location code corresponding to a location of the reference die on the wafermap and determining a physical location of the reference die on the semiconductor wafer using the die detection sensor. The method may further comprise correlating the physical location of the reference die on the semiconductor wafer with the respective location code corresponding to the reference die on the wafermap.
    Type: Application
    Filed: February 2, 2007
    Publication date: August 7, 2008
    Inventors: Melanie Aquitania Pare, Teofilo Froilando Alcantara Bibit-Chee, Mary Amelia Aquino Monis, Melvin B. Alviar, James Raymond Baello, Antonio Rosario Taloban