Patents by Inventor Antonio Vasquez

Antonio Vasquez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967968
    Abstract: A system includes a plurality of digital-to-analog converter (DAC) channels. Each DAC channel includes a current control circuit which receives a start limit signal or an end limit signal. The current control circuit reduces an output current limit of the channel responsive to the start limit signal and increases the output current limit responsive to the end limit signal. Each channel includes a current sensor circuit adapted to measure the output current of the channel and provide a channel over-current alert signal if the output current rises above a high current limit. The system includes a controller which asserts the start limit signal if the number of channels exceeding the high current limit is greater than a maximum allowable number and asserts the end limit signal if the number of channels exceeding the high current limit is less than the maximum allowable number minus a hysteresis value.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: April 23, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Paul Thomas Frost, Aditya Vighnesh Ramakanth Bommireddipalli, Hugo Cheung, Abdullah Yilmaz, Ruben Antonio Vasquez
  • Publication number: 20230246651
    Abstract: A system includes a plurality of digital-to-analog converter (DAC) channels. Each DAC channel includes a current control circuit which receives a start limit signal or an end limit signal. The current control circuit reduces an output current limit of the channel responsive to the start limit signal and increases the output current limit responsive to the end limit signal. Each channel includes a current sensor circuit adapted to measure the output current of the channel and provide a channel over-current alert signal if the output current rises above a high current limit. The system includes a controller which asserts the start limit signal if the number of channels exceeding the high current limit is greater than a maximum allowable number and asserts the end limit signal if the number of channels exceeding the high current limit is less than the maximum allowable number minus a hysteresis value.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 3, 2023
    Inventors: Paul Thomas Frost, Aditya Vighnesh Ramakanth Bommireddipalli, Hugo Cheung, Abdullah Yilmaz, Ruben Antonio Vasquez
  • Patent number: 8600184
    Abstract: A system and method of the present disclosure provides a block, or region, based error diffusion process for reducing artifacts in images. The system and method allows for the generation and the control of the spatial frequency of a masking signal, e.g., noise, in a way that it can be easily passed through the compression process. The system and method provides for selecting a block size of pixels of the image, adding a masking signal to the image, determining a quantization error for at least one block in the image, and distributing the quantization error to neighboring blocks in the image to mask artifacts in the image. An output image is then encoded with a compression function.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: December 3, 2013
    Assignee: Thomson Licensing
    Inventors: Ju Guo, Marco Antonio Vasquez
  • Patent number: 8351730
    Abstract: A system and method for scaling images are provided. An upscaling algorithm or function is employed that increases the size of an image and then filters the upscaled image to remove aliasing artifacts. The system and method provides for acquiring an image of a first size, detecting the geometry of the image, scaling the image to a second size, and filtering the scaled image with at least one filter based on the detected geometry. During the filtering process, the edges of objects in the upscaled image are detected and different filter frequency responses are provided for the detected edges. Providing different filter frequency responses for the detected edges preserves more details for line images.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: January 8, 2013
    Assignee: Thomson Licensing
    Inventors: Dong-Qing Zhang, Ingo Tobias Doser, Marco Antonio Vasquez, Xueming Henry Gu
  • Publication number: 20100260433
    Abstract: A system and method for scaling images are provided. An upscaling algorithm or function is employed that increases the size of an image and then filters the upscaled image to remove aliasing artifacts. The system and method provides for acquiring an image of a first size, detecting the geometry of the image, scaling the image to a second size, and filtering the scaled image with at least one filter based on the detected geometry. During the filtering process, the edges of objects in the upscaled image are detected and different filter frequency responses are provided for the detected edges. Providing different filter frequency responses for the detected edges preserves more details for line images.
    Type: Application
    Filed: September 19, 2007
    Publication date: October 14, 2010
    Inventors: Dong-Qing Zhang, Ingo Tobias Doser, Marco Antonio Vasquez, Xueming Henry Gu
  • Publication number: 20100119173
    Abstract: A system and method of the present disclosure provides a block, or region, based error diffusion process for reducing artifacts in images. The system and method allows for the generation and the control of the spatial frequency of a masking signal, e.g., noise, in a way that it can be easily passed through the compression process. The system and method provides for selecting a block size of pixels of the image, adding a masking signal to the image, determining a quantization error for at least one block in the image, and distributing the quantization error to neighboring blocks in the image to mask artifacts in the image. An output image is then encoded with a compression function.
    Type: Application
    Filed: June 12, 2007
    Publication date: May 13, 2010
    Inventors: Ju Guo, Marco Antonio Vasquez
  • Patent number: 6419973
    Abstract: French fry strips and a related preparation process are provided, wherein the strips are produced from a corn based dough. The corn based dough comprises a matrix of corn meal and corn flour of different particle or granule sizes, admixed with water and optional flavoring and seasoning constituents to form a relatively thick dough having a texture suitable for extruding and cutting to form elongated strips having a size and shape conforming generally to conventional potato-based French fries. The formed and cut corn dough strips may be parfried in hot oil, and then frozen. The frozen corn strips are subsequently finished prepared for consumption, preferably by finish frying in hot oil. The finish prepared corn strips have a corn snack taste in combination with a texture defined by a crispy exterior surface encasing a moist and mealy interior.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: July 16, 2002
    Assignee: J. R. Simplot Company
    Inventors: Peter H. Mattson, John K. Fukushima, Bruce T. Pittard, David B. Walker, Antonio Vasquez
  • Patent number: D819450
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 5, 2018
    Assignee: GABRIELLE STUDIO, INC.
    Inventors: Vicente Antonio Vasquez, Liong The, Soo H. Kim
  • Patent number: D828758
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 18, 2018
    Assignee: GABRIELLE STUDIO, INC.
    Inventors: Vicente Antonio Vasquez, Liong The, Soo H. Kim