Patents by Inventor Antonio Zenteno Ramirez

Antonio Zenteno Ramirez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220094094
    Abstract: In one embodiment, an apparatus includes an integrated circuit (IC) socket and an interposer. The IC socket includes a cavity to receive an IC package including first and second sets of IC contacts, the cavity defined by a base including a set of IC socket interconnects and a frame extending from the base with at least one opening through the frame. The interposer includes a cavity portion disposed adjacent the base of the IC socket, an external portion extending from the cavity portion through one of the at least one opening, at least one connector disposed on the external portion, a first set of interposer interconnects to electrically couple each of the first set of IC contacts with a corresponding one of the set of IC socket interconnects, and a second set of interposer interconnects to electrically couple each of the second set of IC contacts with one of the at least one connector. Other embodiments are described and claimed.
    Type: Application
    Filed: June 11, 2021
    Publication date: March 24, 2022
    Inventors: Ulises Encarnacion, Luis Ricardo Perez Corona, Ricardo Astro Bohorquez, Antonio Zenteno Ramirez, Maria J. Garcia Garcia De Leon
  • Patent number: 10408860
    Abstract: An embodiment includes a system comprising: a polymer substrate including a plurality of voids; and a plurality of metal pins; wherein a first pin, included within the plurality of metal pins, includes: (a)(i) first and second arms that couple to each other by way of an arcuate member, (a)(ii) a middle portion including a middle diameter, a proximal portion including a proximal diameter, and a distal portion including a distal diameter; wherein (b)(i) the middle portion is between the proximal and distal portions, (b)(ii) the middle diameter is less than the proximal and distal diameters, and (b)(iii) the proximal portion, but not the distal portion, is included within one of the plurality of voids. Other embodiments are described herein.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Jorge A. Alvarez Gonzalez, Fernando Gonzalez Lenero, Antonio Zenteno Ramirez, Fernando Mendoza Hernandez
  • Publication number: 20180284156
    Abstract: An embodiment includes a system comprising: a polymer substrate including a plurality of voids; and a plurality of metal pins; wherein a first pin, included within the plurality of metal pins, includes: (a)(i) first and second arms that couple to each other by way of an arcuate member, (a)(ii) a middle portion including a middle diameter, a proximal portion including a proximal diameter, and a distal portion including a distal diameter; wherein (b)(i) the middle portion is between the proximal and distal portions, (b)(ii) the middle diameter is less than the proximal and distal diameters, and (b)(iii) the proximal portion, but not the distal portion, is included within one of the plurality of voids. Other embodiments are described herein.
    Type: Application
    Filed: March 31, 2017
    Publication date: October 4, 2018
    Inventors: Jorge A. Alvarez Gonzalez, Fernando Gonzalez Lenero, Antonio Zenteno Ramirez, Fernando Mendoza Hernandez
  • Patent number: 10078612
    Abstract: An apparatus is described herein. The apparatus includes a plurality of conductors, wherein at least one conductor is a common-mode conductor. The apparatus also includes an encoder to encode data to be transmitted on the plurality of conductors, wherein a data speed of the common-mode conductor is limited and a data speed of other conductors is maximized according to an encoding matrix.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: September 18, 2018
    Assignee: Intel Corporation
    Inventors: Michael W. Leddige, Stephen H. Hall, Chaitanya Sreerama, Olufemi B. Oluwafemi, Antonio Zenteno Ramirez, Maynard C. Falconer
  • Publication number: 20160026597
    Abstract: An apparatus is described herein. The apparatus includes a plurality of conductors, wherein at least one conductor is a common-mode conductor. The apparatus also includes an encoder to encode data to be transmitted on the plurality of conductors, wherein a data speed of the common-mode conductor is limited and a data speed of other conductors is maximized according to an encoding matrix.
    Type: Application
    Filed: July 28, 2014
    Publication date: January 28, 2016
    Inventors: Michael W. Leddige, Stephen H. Hall, Chaitanya Sreerama, Olufemi B. Oluwafemi, Antonio Zenteno Ramirez, Maynard C. Falconer
  • Patent number: 9100047
    Abstract: A method for reducing noise on a power distribution network of a printed circuit board includes determining whether a given data signal may be a problematic data signal. The given data signal is issued onto a signal distribution network of the printed circuit board if the given data signal is determined to not be a problematic data signal. The given data signal is encoded into an encoded data signal if the given data signal is determined to be a problematic data signal, and the encoded data signal is issued onto the signal distribution network.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: August 4, 2015
    Assignee: Intel Corporation
    Inventors: Alberto Alcocer Ochoa, Jose A. Sanchez Sanchez, Dawson W. Kesling, Maynard C. Falconer, Antonio Zenteno Ramirez
  • Publication number: 20150089315
    Abstract: A method for reducing noise on a power distribution network of a printed circuit board includes determining whether a given data signal may be a problematic data signal. The given data signal is issued onto a signal distribution network of the printed circuit board if the given data signal is determined to not be a problematic data signal. The given data signal is encoded into an encoded data signal if the given data signal is determined to be a problematic data signal, and the encoded data signal is issued onto the signal distribution network.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Inventors: Alberto Alcocer Ochoa, Jose Sanchez Sanchez, Dawson Kesling, Maynard Falconer, Antonio Zenteno Ramirez
  • Publication number: 20140181358
    Abstract: Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a signaling module with a receiver, quantizer, and arithmetic circuit. The receiver receives a plurality of encoded line voltages or currents on a plurality of signal lines. The quantizer determines signal levels of each of the plurality of signal lines at a unit interval. The arithmetic circuit provides a plurality of digital output bits of the decoder based on the signal levels. Each one of the digital output bits is a mathematical combination of all of the signal levels.
    Type: Application
    Filed: December 28, 2013
    Publication date: June 26, 2014
    Inventors: Chaitanya Sreerama, Stephen H. Hall, Olufemi OLUWAFEMI, JASON A. Mix, Michael Leddige, Earl J. Wight, Antonio Zenteno Ramirez