Abstract: A programmable data processing apparatus having a bit-plane extraction operation is described, for extracting data from a value of, for example, 32 bits containing 4 bytes, 1a to 1d. Each byte 1a to 1d comprises 8 bits, (a0-a7, b0-b7, c0-c7 and d0-d7, respectively). The bit-plane extraction operation retrieves one bit from each of these bytes, for example the second bit (a1, b1, c1, d1), which is specified by an argument. The operation involves concatenating these bits (a1, b1, c1, d1) and returning a result value 5. Depending on the particular data processing application, the result value may be bit-reversed to provide a result value 7 (for example, if a bit-reversal is required to deal with endianness, or other reasons). The bit-plane extraction operation can be used as a pre-processing operation in data processing operations such as “sum-of-absolute-differences” in the processing of video data.

Abstract: A data processing circuit comprises a register file (14) having read ports and write ports. A plurality of functional units (21a-c), is coupled to receive operand data from a same combination of read ports. Each functional unit is coupled to a respective one of the write ports for writing a respective result. An instruction issue slot has outputs (11) for supplying register selection information to said combination read ports and to the respective ones of the write ports. The output of the issue slot also supplies an operation code. The functional units (21a-c) in the plurality are arranged to respond to at least to one value of the operation code by each executing a respective operation using the same operands from said same combination and each functional unit producing a respective result at a respective ones of the write ports.

Abstract: A data processing circuit comprises a register file (14) having read ports and write ports. A plurality of functional units (21 a-c), is coupled to receive operand data from a same combination of read ports. Each functional unit is coupled to a respective one of the write ports for writing a respective result. An instruction issue slot has outputs (11) for supplying register selection information to said combination read ports and to the respective ones of the write ports. The output of the issue slot also supplies an operation code. The functional units (21 a-c) in the plurality are arranged to respond to at least to one value of the operation code by each executing a respective operation using the same operands from said same combination and each functional unit producing a respective result at a respective ones of the write ports.

Abstract: A programmable data processing apparatus having a bit-plane extraction operation is described, for extracting data from a value of, for example, 32 bits containing 4 bytes, 1a to 1d. Each byte 1a to 1d comprises 8 bits, (a0-a7, b0-b7, c0-c7 and d0-d7, respectively). The bit-plane extraction operation retrieves one bit from each of these bytes, for example the second bit (a1, b1, c1, d1), which is specified by an argument. The operation involves concatenating these bits (a1, b1, c1, d1) and returning a result value 5. Depending on the particular data processing application, the result value may be bit-reversed to provide a result value 7 (for example, if a bit-reversal is required to deal with endianness, or other reasons). The bit-plane extraction operation can be used as a pre-processing operation in data processing operations such as “sum-of-absolute-differences” in the processing of video data.