Abstract: A computing system comprises one or more multicore processor(s) comprising a set of multiple processing units each operable at a variable frequency, and a main memory operable at a variable frequency. A feedback controller is configured to control the frequency of each processing unit of the set and the frequency of the main memory dependent on a measure representative of a current performance of an application running on one or more of the multiple processing units of the set.

Abstract: A computing system comprises one or more multicore processor(s) comprising a set of multiple processing units each operable at a variable frequency, and a main memory operable at a variable frequency. A feedback controller is configured to control the frequency of each processing unit of the set and the frequency of the main memory dependent on a measure representative of a current performance of an application running on one or more of the multiple processing units of the set.

Abstract: In some embodiments of this disclosure, a computer-implemented method includes accessing a set of two or more activity logs associated with two or more virtual machines, each activity log being associated with a corresponding virtual machine. A computational capacity is calculated, by a computer processor, for each of the virtual machines based at least in part on the activity logs. A rank is calculated for each of the virtual machines, where a first rank calculated for a first virtual machine is based, at least in part, on a monetary cost of the first virtual machine and the calculated computational capacity of the first virtual machine.

Abstract: A method of distributed memory access in a network, the network including a plurality of distributed compute elements, at least one control element and a plurality of distributed memory elements, wherein a data element is striped into data segments, the data segments being imported on at least a number of the distributed memory elements by multiple paths in the network, includes receiving, by a requesting element, credentials including an access permission for accessing the number of distributed memory elements and location information from the control element, the location information indicating physical locations of the data segments on the number of distributed memory elements; and launching, by the requesting element, a plurality of data transfers of the data segments over the multiple paths in the network to and/or from the physical locations.

Abstract: The invention relates to a switching device which transports data packets from input ports to selected output ports. The payload of the packets is stored in a storage means. A switching means is arranged which has more switch outputs than switch inputs and which switches sequentially between one switch input and several switch outputs while storing the payloads. Furthermore, the invention relates to a storing method which uses switching means to store payloads in a sequential order and to a switching apparatus comprising several switching devices. Furthermore, the invention relates to systems using the switching device as a scaleable module.

Abstract: A modular approach to the mapping of data in and from a standard SDH/SONET signal is described. A module has interfaces (T0-T8) which allows to connect to it to other of its kind and thereby achieving higher data rates, i.e. access to standard signals of higher levels. By choosing among different interconnection schemes, arrangements comprising a plurality of modules are also able to support concatenated data traffic.

Abstract: In a switching system interconnecting transmission links (21-i, 23-i) on which circuit switched (CS) and packet switched (PS) information is transferred, a switch fabric (11) is provided which interconnects a plurality of input ports (15-i) to a plurality of output ports (19-i). The information arriving on incoming links is converted in switch adapters (13-i) to uniform minipackets, each having a routing address designating the required output port. The switch fabric consists of parallel equal switching slices, e.g. binary routing trees (71), which transfer in a non-blocking manner each minipacket from its input port to one output port in response to the routing address. Collecting means (73, 75) are provided at each output port for accepting the minipackets arriving from the different input ports.