Abstract: An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.

Abstract: A data processing apparatus and method of handling write transactions in such an apparatus is provided. The apparatus has a plurality of devices, and bus circuitry providing connection paths between the plurality of devices. At least one of the devices has a bus master interface operable to generate write transactions for output via the bus circuitry, whilst at least one of the devices has a bus slave interface operable to receive the write transactions from the bus circuitry. A write transaction includes transferring a write address from a bus master interface to a bus slave interface and separately transferring write data from the bus master interface to the bus slave interface. In accordance with embodiments of the present invention, the bus master interface is allowed to generate a write transaction such that the write data is received at the bus slave interface before the associated write address. This leads to a significant decrease in the complexity of the apparatus.

Abstract: An apparatus for arbitration within a data processing apparatus between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit. The plurality of paths include a shared connection, the data processing apparatus having a plurality of initiator logic elements for initiating transfers and a plurality of recipient logic elements for receiving transfers, for each transfer the corresponding path coupling the initiator logic element responsible for initiating that transfer with the recipient logic element destined to receive that transfer. The apparatus provides arbitration logic with an indication as to whether the ready signal from a storage element has been asserted, and employs the arbitration logic to select, in dependence on predetermined criteria including at least that indication, one of the plurality of transfers for routing via the shared connection.

Abstract: A bus master 2, 4 sends write transactions to a bus slave 8 which include separate write addresses AW and write data WD. Write transaction identifiers AWID, WID are associated with these write addresses and write data. The bus slave can accept multiple write addresses such that there can be copending write transactions to the same bus slave. The bus slave uses the write transaction identifiers to correlate interleaved write data for the co-pending write transactions with their write addresses.

Abstract: An integrated circuit 2 is provided with multiple bus masters 4, 6 and multiple bus slaves 8, 10, 12, communicating via a multi-channel communication bus. A separate write data channel, read data channel and write response channel are provided as well as a separate write address channel and a read address channel. The provision of a dedicated write response channel frees the read data channel to be more efficiently used for the transfer of read data. Transactions may be burst mode transactions with a single write response corresponding to the write transaction as a whole.

Abstract: A data processing system is provided with a bus having separate write channels W and read channels R via which bus transactions are made. Bus transaction buffers 34 are provided within the bus structure to buffer write requests, particularly so as to alleviate problems associated with relatively slow bus slaves. The bus transaction buffers 34 are responsive to the memory addresses associated with write requests and read requests which pass through them to identify those to the same memory address, or memory addresses within a predetermined range, so as to either ensure a strict correct ordering of those transactions, read to follow write, or to satisfy a read following a write with a buffered write data value and then flushing the read request such that it does not reach its final destination.

Abstract: A method of arbitration within a data processing apparatus between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit. The plurality of paths include a shared connection, the data processing apparatus having a plurality of initiator logic elements for initiating transfers and a plurality of recipient logic elements for receiving transfers, for each transfer the corresponding path coupling the initiator logic element responsible for initiating that transfer with the recipient logic element destined to receive that transfer. The method comprises the steps of providing to arbitration logic an indication as to whether the ready signal from a storage element has been asserted, and employing the arbitration logic to select, in dependence on predetermined criteria including at least that indication, one of the plurality of transfers for routing via the shared connection.

Abstract: A method and design tool are provided for modifying a design of a bus interconnect block for a data processing apparatus in order to meet a requirement for a chosen characteristic of the bus interconnect block. The bus interconnect block provides a plurality of connections via which one or more master devices may access one or more slave devices, each connection comprising one or more paths, and each path having one or more path portions separated by storage elements. The method comprises the steps of: (a) selecting one or more candidate paths from said paths; (b) for each candidate path, applying predetermined criteria to determine whether modification of the number of storage elements in said path will assist in meeting the requirement for said chosen characteristic; and (c) modifying the number of storage elements in each candidate path for which it is determined at said step (b) that modification will assist in meeting the requirement for said chosen characteristic.

Abstract: A data processing apparatus and method of configuration of such an apparatus are provided, the apparatus comprising a plurality of logic elements for processing data, a plurality of storage elements for temporarily storing data, and a plurality of connections from which data is passed between the logic elements. Each connection comprises one or more path portions separated by the storage elements. A number of the storage elements are selectable storage elements having a bypass path associated therewith, and a controller is provided for controlling the selection of each selectable storage element or its associated bypass path based on setup information, in order to enable a change in the number of path portions within one or more of the connections.

Abstract: A method and design tool are provided for modifying a design of a bus interconnect block for a data processing apparatus in order to meet a requirement for a chosen characteristic of the bus interconnect block. The bus interconnect block provides a plurality of connections via which one or more master devices may access one or more slave devices, each connection comprising one or more paths, and each path having one or more path portions separated by storage elements. The method comprises the steps of: (a) selecting one or more candidate paths from said paths; (b) for each candidate path, applying predetermined criteria to determine whether modification of the number of storage elements in said path will assist in meeting the requirement for said chosen characteristic; and (c) modifying the number of storage elements in each candidate path for which it is determined at said step (b) that modification will assist in meeting the requirement for said chosen characteristic.

Abstract: A data processing apparatus and method of configuration of such an apparatus are provided, the apparatus comprising a plurality of logic elements for processing data, a plurality of storage elements for temporarily storing data, and a plurality of connections from which data is passed between the logic elements. Each connection comprises one or more path portions separated by the storage elements. A number of the storage elements are selectable storage elements having a bypass path associated therewith, and a controller is provided for controlling the selection of each selectable storage element or its associated bypass path based on setup information, in order to enable a change in the number of path portions within one or more of the connections.