Abstract: An internal clock signal disable circuit is disclosed for disabling an internal clock signal used in a synchronous static random access memory (SRAM). The reduced power mode is preferably a sleep mode commanded by assertion of a reduced power command signal, which may be a Jedec-standard "ZZ" signal. The disable circuit includes a pair of latch devices clocked by clock signals deriving from the external clock signal applied to the SRAM. The ZZ signal is applied to the input of the first latch, whose output is connected to the input of the second latch. The output of the second latch is processed to generate disable signals for disabling generation of the internal clock signal used on the device. The pair of latches insures that a delay is introduced prior to disabling the internal clock so that at least one clock pulse of the internal clock signal is generated before the internal clock is shut down.