Abstract: There is provided a dual-slope analog-to-digital converter (ADC), comprising an input signal terminal, configured to provide an analog signal, and a reference signal terminal, configured to provide a predetermined reference signal. The ADC further comprises an integrator, that is operatively coupled to said input signal terminal and said reference signal terminal via a first switch unit, said first switch unit being configured to selectively connect and disconnect said integrator to and from any one of said input signal terminal and said reference signal terminal.

Abstract: A signal measuring apparatus comprising: signal circuitry configured to receive an input signal to be measured; and memory circuitry coupled to the signal circuitry and configured to store information representing a magnitude of a voltage or a current of the input signal; wherein the memory circuitry comprises a first memory cell having a material which is arranged to switch from a first material state to a second material state in response to a first switching signal being applied thereto, wherein the first memory cell is tuned to a first value for the first switching signal so that a current or voltage with a magnitude at or above the first value will cause the material of the first memory cell to switch from the first material state to second material state; wherein the apparatus is configured to apply a measurement signal indicative of the input signal to the first memory cell for switching the material of the first memory cell from the first material state to the second material state in dependence on a

Abstract: There is provided a dual-slope analog-to-digital converter (ADC), comprising an input signal terminal, configured to provide an analog signal, and a reference signal terminal, configured to provide a predetermined reference signal. The ADC further comprises an integrator, that is operatively coupled to said input signal terminal and said reference signal terminal via a first switch unit, said first switch unit being configured to selectively connect and disconnect said integrator to and from any one of said input signal terminal and said reference signal terminal.

Abstract: Clock recovery circuitry for recovering a clock signal from a data signal is disclosed. The clock recovery circuitry comprises sampling unit (46) for sampling the data signal at a plurality of sampling points, bit reversal detecting unit (48) for determining a sampling point at which the data signal changes state, selecting unit (50) for selecting a phase from amongst a plurality of candidate phases based on a sampling point at which the data signal is determined to change state, and phase setting unit (38) for setting the phase of the clock signal. The circuitry may be used to produce an estimate of a desired phase of the clock signal for supply to a phase locked loop. This can allow the phase locked loop to be brought quickly into lock.

Abstract: A first transparent latch receives a first synchronised signal changing its logic state synchronously with respect to a clock signal. A second transparent latch receives a second synchronised signal output by the first latch. When the clock signal has a first logic state the first latch has a non-responsive state and the second latch has a responsive state, and when the clock signal has a second logic state the first latch has the responsive state and the second latch has the non-responsive state. The change in logic state of a third synchronised signal output by the second latch is guaranteed to occur in a particular half-cycle of the clock signal, irrespective of process/voltage/temperature (PVT) variations of the circuitry.

Abstract: The present invention relates to a method of sampling a received digital data stream. The method comprises: generating a first sampling clock in dependence on a detected rate of said received digital data stream for sampling at a first time within a bit period of said received digital data stream; detecting a shape of a data eye of data within said received digital data stream; and generating a second sampling clock interleaved with said first sampling clock for sampling at a second different time within a bit period the second sampling clock being offset from said first sampling clock by an amount dependent on the detected shape of the data eye.

Abstract: Clock recovery circuitry for recovering a clock signal from a data signal is disclosed. The clock recovery circuitry comprises sampling means (46) for sampling the data signal at a plurality of sampling points, bit reversal detecting means (48) for determining a sampling point at which the data signal changes state, selecting means (50) for selecting a phase from amongst a plurality of candidate phases based on a sampling point at which the data signal is determined to change state, and phase setting means (38) for setting the phase of the clock signal in dependence on the selected phase. The circuitry may be used to produce an estimate of a desired phase of the clock signal for supply to a phase locked loop. This can allow the phase locked loop to be brought quickly into lock.

Abstract: A first transparent latch (22) receives a first synchronised signal (S1) which changes its logic state synchronously with respect to a clock signal (CLK). A second transparent latch (24) receives a second synchronised signal (S2) output by the first latch (22). When the clock signal has a first logic state (H) the first latch (22) has a non-responsive state and the second latch has a responsive state, and when the clock signal has a second logic state (L) the first latch has the responsive state and the second latch has the non-responsive state.